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33793 Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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33793 Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
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10 / 27 page ![]() Analog Integrated Circuit Device Data 10 Freescale Semiconductor 33793 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33793 is designed to be used with a sensor at a location that is remote from a centralized MCU. This device provides power, measurement, and communications between the remote sensor and the centralized MCU over a DSI bus. Sensors such as accelerometers can be powered from the regulated output of the device, and the resulting analog value from the sensor can be converted from an analog level to a digital value for transmission over the DSI bus in response to a query from the MCU. Four I/O lines can be configured by the central MCU over the DSI bus as analog inputs, digital inputs, or digital outputs. This allows more than one sensor to be remotely controlled and measured by a single 33793. Additionally, a high drive logic output is provided that can be used to power other low-power sensors. Power is passed from BUSIN or BUSOUT through on- board rectifiers to a storage capacitor (referred to as the H_CAP). The H_CAP stores energy during the highest voltage excursions of the BUSIN or BUSOUT pin (idle) and supplies energy to power the device during low excursions of BUSIN and BUSOUT. The Regulator supplies an on-board regulated voltage for internal use, and the Power on Reset (POR) circuit provides a reset signal during low-voltage conditions and during power up/down. Some current is available for low-power sensors. Data from the Central Control Unit (CCU) is applied to the BUSIN and/or BUSOUT pins as voltage levels that are sensed by the Level Detection circuitry. The Serial Decoder detects these transitions and decodes the incoming data. The Control Logic provides overall control of the 33793. It controls diagnostic testing and formats responses to commands with the message encoder. Responses are formed via a switched current source that is slew-rate controlled. The one-time programmable (OTP) memory array provides the nonvolatile storage for the pre-programmed address. It is accessed via the Read/Write NVM command. It has a built-in hardware lock that only allows one write. FUNCTIONAL PIN DESCRIPTION BUS RETURN (BUSRTN) This pin provides the common return for power and signalling. INPUT/OUTPUT (I/O0, I/O1, I/O2, I/O3) This pin can be used to provide a logic level output, a logic input, or an analog-to-digital (A/D) input. ANALOG GROUND (AGND) This pin is the low reference level and power return for the analog-to-digital converter (ADC). LOGIC OUT (LOGOUT) This is a logic output with higher pull-up drive capability than the standard logic I/O. REGULATOR OUTPUT (REGOUT) This pin provides a regulated 5.0 V output. The power is derived from the bus. HOLDING CAPACITOR (H_CAP) A capacitor attached to this pin is charged by the bus during bus idle and supplies current to run the device and for external devices via the REGOUT pin during non-idle periods. DSI BUS INPUT (BUSIN) This pin attaches to the bus and responds to initialization commands. DSI BUS OUTPUT (BUSOUT) This pin attaches to the bus and responds to reverse initialization commands. FUNCTIONAL INTERNAL BLOCK DESCRIPTION Refer to Figure 2, 33793 Internal Block Diagram, page 3, for a simplified representation of the 33793’s components. RECTIFIER This rectifier or switch peak detects the bus signal into an external capacitor attached to H_CAP. The capacitor supplies power during signaling while the input voltage is at a lower level. The voltage waveform at BUSIN and/or BUSOUT and the size of the filter capacitor at H_CAP must be such that the voltage at H_CAP will not drop below the frame threshold during signaling. POR The 33793 leaves the reset state when the voltage on H_CAP rises above the Power-ON Reset threshold. TIMEOUT A timeout timer keeps track of the length of the time when the input is not in idle mode. If this time exceeds a limit, the |
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