33797 datasheet(13/34 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33797

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics

Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V; 7.0 V ≤ VVFIRE_XX ≤ 35 V; VVDIAG_X = VVFIRE_XX; FEN 1 = FEN 2

= VDD; RR_LIMIT_X = 10 kΩ ±1%, RR_DIAG = 10 kΩ ±1%, -40°C ≤ TA ≤ +85°C, GND = 0 unless otherwise noted. Typical values

noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

SERIAL INTERFACE

CLK Cycle Time (1/FCLK) (18)

tCYC

200

–

CLK High Time (18)

VCLK > VDD x 70%

tHI

–

CLK Low Time (18)

VCLK < VDD x 20%

tLO

–

Clock Rise Time (18)

VCLK = 20% VDD to 70% VDD, CLOAD = 100 pF

tRISE

–

Clock Fall Time (18)

VCLK = 70% VDD to 20% VDD, CLOAD = 100 pF

tFALL

–

Data Out Rise Time (19)

VDO = 20% VDD to 70% VDD, CLOAD = 100 pF

–

Data Out Fall Time (19)

VDO = 70% VDD to 20% VDD, CLOAD = 100 pF

–

Chip Select Setup Time (19)

CSB

Before CLK

tLEAD

–

Chip Select Hold Time (19)

CLK

Before CSB

tLAG

–

Data In Setup Time (19)

D1 Valid Before CLK

tSU

–

Data In Hold Time (19)

D1 Hold Time After CLK

↑

–

Data Out Access Time (19)

CSB

to D0 Valid

–

Data Out Disable Time (19)

CSB

↑ to D0 HI-Z

tDIS

–

Data Out Valid Time (19)

CLK

↑ to D0 Valid, C

LOAD = 100 pF

–

Data Out Hold Time (19)

D0 held After CLK

↑

tHO

0.0

–

Diagnostic Delay Time (Between Two Successive Commands)

tDIAG

2.5

–

µs

Notes

Determined by Design

Guaranteed by Characterization

↓

↑

↓

↑

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