33976_07 datasheet(13/41 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33976

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

DATA INPUT

The Input Shift register captures data at the falling edge of

the SCLK clock. The SCLK clock pulses exactly 16 times only

inside the transmission windows (CS in a logic [0] state). By

the time the CS signal goes to logic [1] again, the contents of

the Input Shift register are transferred to the appropriate

internal register addressed in bits 15:13. The minimum time

should be kept high depends on the internal clock speed,

specified in the SPI INTERFACE TIMING (17) section of the

Static Electrical Characteristics, found on page 6. It must be

long enough so the internal clock is able to capture the data

from the Input Shift register and transfer it to the internal

registers.

DATA OUTPUT

At the first rising edge of the SCLK clock, with CS at

logic [0], the contents of the selected Status Word register

are transferred to the Output Shift register. The first 16 bits

clocked out are the status bits. If data continues to clock in

before the CS transitions to a logic [1], the device begins to

shift out the data previously clocked in FIFO after the CS first

transitioned to logic [0].

LOGIC COMMANDS AND REGISTERS

COMMUNICATION MEMORY MAPS AND REGISTER DESCRIPTIONS

The 33976 device is capable of interfacing directly with a

microcontroller via the 16-bit SPI protocol specified below.

The device is controlled by the microprocessor and reports

back status information via the SPI. This section provides a

detailed description of all registers accessible via serial

interface. The various registers control the behavior of this

device.

A message is transmitted by the master beginning with the

MSB (D15) and ending with the LSB (D0). Multiple messages

can be transmitted in succession to accommodate those

applications where daisy chaining is desirable, or to confirm

transmitted data, as long as the messages are all multiples of

16 bits. Data is transferred through daisy-chained devices, as

illustrated in Figure 7, page 12. If an attempt is made to latch

in a message smaller than 16 bits wide, it is ignored.

Table 6 lists the seven registers the 33976 uses to

configure the device, control the state of the four H-bridge

outputs, and determine the type of status information that is

clocked back to the master. The registers are addressed via

D15:D13 of the incoming SPI word.

MODULE MEMORY MAP

Various registers of the 33976 SPI module are addressed

by the three MSBs of the 16-bit word received serially.

Functions to be controlled include:

• Individual gauge drive enabling

• Power-up/down

• Internal clock calibration

• Gauge pointer position and velocity

• Gauge pointer zeroing

• Air core motor movement emulation

• Status information

Status reporting includes:

• Individual gauge overtemperature condition

• Battery overvoltage

• Battery undervoltage

• Pointer zeroing status

• Internal clock status

• Confirmation of coil output changes that should result in

pointer movement

• Real time pointer position information

• Real time pointer velocity step information

• Pointer movement direction

• Command pointer position status

• RTZ accumulator value

The following section describes the registers, their

addresses, and their impact on device operation.

Address 000—Power, Enable, Calibration, and

Configuration Register (PECCR)

The Power, Enable, Calibration, and Configuration

33976 using this register allows the master to

(1) independently enable or disable the output drivers of the

two-gauge controllers, (2) calibrate the internal clock,

(3) disable the air core emulation, (4) select the direction of

the pointer movement during pointer positioning and zeroing,

(5) configure the device for the desired status information to

Table 6. Module Memory Map

Address

[15:13]

Name

See Page

000

Power, Enable, Calibration,

and Configuration Register

PECCR

Page 13

001

Maximum Velocity Register

VELR

Page 15

010

Gauge 0 Position Register

POS0R

Page 16

011

Gauge 1 Position Register

POS1R

Page 16

100

Return to 0 Register

RTZR

Page 16

101

Return to 0

Configuration Register

RTZCR

Page 17

110

Ramp Selection Register

RMPSELR

Page 19

111

Reserved for Test

–

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