Analog Integrated Circuit Device Data

Freescale Semiconductor

13

33990

TYPICAL APPLICATIONS

FUNCTIONAL PIN DESCRIPTION

transition before 96

µs, one logic state is inferred. If there is a

bus transition after 96

µs, the other logic state is inferred. The

“end of data” bit is a logic [0] and lasts 200

µs. If there is no

activity on the bus for 280

µs to 320 µs following a broadcast

message, multiple unit nodes may arbitrate for control of the

next message. During an arbitration, after the “start of frame”

bit has been transmitted, the secondary node transmitting the

most consecutive logic [0] bits will be granted sole

transmission access to the bus for that message.

Loss of Assembly Ground Connection

The definition of a loss of assembly ground condition at the

device level is that all pins of the 33990, with the exception of

The LOAD pin of the device has an internal transistor

switch connected to it that is normally saturated to ground.

This pulls the LOAD-side of the external resistor (tied from

BUS to LOAD) to ground under normal conditions. The LOAD

pin switch is essentially that of an “upside down” FET, which

is normally biased “on” so long as module ground is present

and biased “off” when loss-of-ground occurs. When a loss of

assembly ground occurs, the load transistor switch is self-

biased “off”, allowing no more than 100

µA of leakage current

to flow in the LOAD pin. During such a loss of assembly

ground condition, the BUS and LOAD pins exhibit a high

sourcing any current or loading the bus, which would cause a

corruption of any data being transmitted on the bus. While a

particular assembly is experiencing a loss of ground, all other

assembly nodes are permitted to function normally. It should

be noted that with other nodes existing on the bus, the bus

will always have some minimum/maximum impedance to

ground as shown in Table 6, page 11.

Loss of Assembly Battery Connection

The definition of a loss of assembly battery condition at the

between these pins and ground.

Figure 14. Typical Application

BUS

+VBAT

SLEEP

TX

RX

4X/LOOP

GND

LOAD

Primary

Node

MCU

Secondary

Nodes

33990

10.6

k

Ω

470pF

47