MPC8250VR datasheet(17/60 Pages) FREESCALE

17 / 60 page

MPC8250 Hardware Specifications, Rev. 1

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 10 lists SIU output characteristics.

NOTE

Activating data pipelining (setting BRx[DR] in the memory controller)

improves the AC timing. When data pipelining is activated, sp12 can be

used for data bus setup even when ECC or PARITY are used. Also, sp33a

can be used as the AC specification for DP signals.

Table 10. AC Characteristics for SIU Outputs 1

Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

Spec Number

Characteristic

Max Delay (ns)

Min Delay (ns)

Max

Min

66 MHz 83 MHz 66 MHz 83 MHz

sp31

sp30

PSDVAL/TEA/TA

0.5

sp32

sp30

ADD/ADD_atr./BADDR/CI/GBL/WT

6.5

0.5

sp33a

sp30

Data bus

6.5

0.5

sp33b

sp30

0.5

sp34

sp30

Memory controller signals/ALE

0.5

sp35

sp30

All other signals

5.5

0.5

MPC8250VR Datasheet(PDF) 17 Page - Freescale Semiconductor, Inc

MPC8250VR Datasheet(HTML) 17 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL