XRT83VSH314 datasheet(21/80 Pages) EXAR

21 / 80 page

XRT83VSH314

REV. 1.0.1

14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

3.2

Clock and Data Recovery

The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the

incoming data stream and outputs a clock that’s in phase with the incoming signal. This allows for multi-

channel T1/E1/J1 signals to arrive from different timing sources and remain independent. In the absence of an

incoming signal, RCLK maintains its timing by using the internal master clock as its reference. The recovered

data can be updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To

update data on the falling edge of RCLK, set RCLKE to "1" in the appropriate global register. Figure 5 is a

timing diagram of the receive data updated on the rising edge of RCLK. Figure 6 is a timing diagram of the

receive data updated on the falling edge of RCLK. The timing specifications are shown in Table 4.

TABLE 3: RECEIVE TERMINATIONS

RXTSEL

TERSEL1

TERSEL0

RXRES1

RXRES0

Rext

Rint

MODE

Rext

∞

T1/E1/J1

∞

100

Ω

∞

110

Ω

∞

Ω

∞

120

Ω

240

Ω

172

Ω

240

Ω

204

Ω

240

Ω

108

Ω

240

Ω

240

Ω

210

Ω

192

Ω

210

Ω

232

Ω

210

Ω

116

Ω

210

Ω

280

Ω

150

Ω

300

Ω

150

Ω

412

Ω

150

Ω

150

Ω

150

Ω

600

Ω

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