XRD9814B datasheet(9/53 Pages) EXAR

9 / 53 page

XRD9814B/9816B

Rev. 1.00

ELECTRICAL CHARACTERISTICS (CONT’D)

AVDD=DVDD=5.0V, ADCCLK=6MHz, Ta=25C unless otherwise specified

Parameter

Symbol

Min

Typ

Max

Unit

Conditions

TIMING SPECIFICATIONS

ADCCLK Pulse Width

taclk

66.5

BSAMP falling edge delay from

tbfcr

rising ADCCLK

BSAMP falling edge to VSAMP

tbvf

falling edge.

ADCCLK Period (1 Ch. Mode)

tcp1

166

ADCCLK Period (3 Ch. Mode)

tcp3

133

1-Channel Conversion Period

tcr1

166

3-Channel Conversion Period

tcr3

400

BSAMP Pulse Width

tpwb

VSAMP Pulse Width

tpwv

VSAMP falling edge to BSAMP

tvbf

falling edge.

VSAMP falling edge delay from

tvfcr

All modes except 1-Channel

rising ADCCLK.

S/H

VSAMP falling edge delay

tvfcr

1-Channel S/H, Config

from rising ADCCLK

REG #1, PB2=1, PB7=1

PGA Settling Time

tstl

Aperture Delay

tap

VSAMP TIMING OPTION #1

VSAMP rising edge delay from

tvrcf

tvrcr is not required, Config

falling ADCCLK (Note 1)

REG #1, PB0=0

VSAMP TIMING OPTION #2

VSAMP rising edge delay from

tvrcr

tvrcf is not required, Config

rising ADCCLK (Note 1)

REG # 1, PB0=1

WRITE SPECIFICATIONS

Data Setup Time

tds

Data Hold Time

tdh

Load Setup Time

tlcs

Load Hold Time

tlch

Load Pulse Width

tplw

Note 1:

VSAMP Timing Option #2 allows additional timing flexibility by allowing the rising edge of VSAMP to occur

approximately one-half ADCCLK period earlier than Option #1. Option #2 is only available in 3-Channel

Operation (PB4=0, PB3=0, Configuration Register #1).

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