SAA7740H datasheet(21/28 Pages) PHILIPS

21 / 28 page

1997 May 30

Philips Semiconductors

Product speciﬁcation

Digital Audio Processing IC (DAPIC)

SAA7740H

I2C-BUS PROTOCOL

The I2C-bus is intended for 2-way, 2-line communication

between different ICs or modules. The two lines are the

serial data line (SDA) and the serial clock line (SCL). Both

lines must be connected to the supply rail via a pull-up

resistor when connected to the output stages of a

microcontroller. Data transfer can only be initiated when

the bus is not busy. Full details of the I2C-bus are given in

the document

“The I2C-bus and how to use it”. This

document may be ordered using the code

9398 393 40011.

Bit transfer

One data bit is transferred during each clock pulse.

The data on the SDA line must remain stable during the

HIGH period of the clock pulses as changes in the data line

at this time will be interpreted as control signals.

The maximum clock frequency is 100 kHz (see Fig.12).

START and STOP condition

In the START and STOP condition the data and clock lines

remain HIGH when the bus is not busy. A HIGH-to-LOW

transition on the data line, while the clock is HIGH, is

defined as the START condition (S). A LOW-to-HIGH

transition on the data line, while the clock is HIGH, is

defined as the STOP condition (P); (see Fig.13).

Data transfer

A device generating a message is a ‘transmitter’, a device

receiving a message is a ‘receiver’. The device that

controls the message is the ‘master’ and the devices which

are controlled by the device are the ‘slaves’ (see Fig.14).

Acknowledge

The number of data bytes that are transferred between the

START and STOP conditions, from transmitter to receiver,

is unlimited. Each byte is followed by an acknowledge bit.

The acknowledge bit is a HIGH level bit placed on the bus

by the transmitter, whereas the master generates an extra

acknowledge bit which is related to the clock pulse. A slave

receiver which is addressed must generate an

acknowledge bit after the reception of each byte.

The master must also generate an acknowledge bit after

the reception of each byte that has been clocked out of the

slave transmitter.

The device that acknowledges has to pull down the SDA

line during the acknowledge clock pulse so that the SDA

line is stable LOW during the HIGH period of the

acknowledge related clock pulse. Set-up and hold times

must also be taken into account. A master receiver must

signal an end-of-data to the transmitter. This is achieved

by not generating an acknowledge on the last byte that has

been clocked out of the slave. In this condition the

transmitter must leave the data line HIGH to enable the

master to generate a STOP condition (see Fig.15).

Fig.12 Bit transfer on the I2C bus.

handbook, full pagewidth

MLC160

SDA

SCL

data line

stable

data valid

change

of data

allowed

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