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SST26VF016B Datasheet(PDF) 13 Page - Microchip Technology

Part # SST26VF016B
Description  2.5V/3.0V 16-Mbit Serial Quad I/O™ (SQI™) Flash Memory
PDF  84 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

SST26VF016B Datasheet(HTML) 13 Page - Microchip Technology

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2014-2022 Microchip Technology Inc. and its subsidiaries
DS20005262G-page 13
SST26VF016B
Identification
JEDEC-ID
JEDEC-ID Read
9FH
X
0
0
3 to ∞
104 MHz/
80 MHz
Quad J-ID
Quad I/O J-ID Read
AFH
X
0
1
3 to ∞
SFDP
Serial Flash Discoverable
Parameters
5AH
X
3
1
1 to ∞
Write
WREN
Write Enable
06H
X
X
0
0
0
104 MHz/
80 MHz
WRDI
Write Disable
04H
X
X
0
0
0
SE(11)
Erase 4 Kbytes of Memory
Array
20H
X
X
3
0
0
BE(12)
Erase 64, 32 or 8 Kbytes of
Memory Array
D8H
X
X
3
0
0
CE
Erase Full Array
C7H
X
X
0
0
0
PP
Page Program
02H
X
X
3
0
1 to 256
SPI Quad
PP(7)
SQI Quad Page Program
32H
X
3
0
1 to 256
WRSU
Suspends Program/Erase
B0H
X
X
0
0
0
104 MHz/
80 MHz
WRRE
Resumes Program/Erase
30H
X
X
0
0
0
TABLE 5-1:
DEVICE OPERATION INSTRUCTIONS FOR SST26VF016B (CONTINUED)
Instruction
Description
Command
Cycle(1)
Mode
Address
Cycle(s)(2,3)
Dummy
Cycle(s)(3)
Data
Cycle(s)(3)
Max
Freq(4)
SPI SQI
Note 1: Command cycle is two-clock periods in SQI mode and eight-clock periods in SPI mode.
2: Address bits above the Most Significant bit of each density can be VIL or VIH.
3: Address, Dummy/Mode bits and Data cycles are two-clock periods in SQI and eight-clock periods in SPI
mode.
4: The maximum frequency for all instructions is up to 104 MHz from 2.7V to 3.6V and up to 80 MHz from
2.3V to 3.6V unless otherwise noted. For extended temperature (+125°C), the maximum frequency is up
to 80 MHz.
5: RST command only executed if RSTEN command is executed first. Any intervening command will disable
Reset.
6: Device accepts eight-clock command in SPI mode or two-clock command in SQI mode.
7: Data cycles are two-clock periods. IOC bit must be set to ‘1’ before issuing the command.
8: Address, Dummy/Mode bits and data cycles are two-clock periods. IOC bit must be set to ‘1’ before issu-
ing the command.
9: Data cycles are four-clock periods.
10: Address, Dummy/Mode bits and Data cycles are four-clock periods.
11: Sector Addresses: Use AMS-A12, remaining address are “don’t care”, but must be set to VIL or VIH.
12: Blocks are 64-Kbyte, 32-Kbyte or 8-Kbyte, depending on location. Block Erase Address: AMS-A16 for
64-Kbyte; AMS-A15 for 32-Kbyte; AMS-A13 for 8-Kbyte. Remaining addresses are “don’t care”, but must be
set to VIL or VIH.



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