DS28EC20 datasheet(13/28 Pages) AD

13 / 28 page

DS28EC20

Analog Devices, Inc.

13 of 28

Figure 7-1. Memory Function Flowchart

0Fh

Write Scratch-

pad?

Bus Controller TX EEPROM

Array Target Address

TA1 (T[7:0]), TA2 (T[15:8])

To Figure 7,

2nd Part

From Figure 7,

2nd Part

Bus Controller TX Memory

Function Command

To ROM Functions

Flow Chart (Figure 9)

From ROM Functions

Flow Chart (Figure 9)

Controller

TX Reset?

Controller TX Data Byte

to Scratchpad Offset

DS28EC20 sets Scratch-

pad Offset = (T[4:0]),

Clears PF, AA, BS

Scrpad. Offset

= 11111b?

DS28EC20 TX CRC16 of

Command, Address, Data

Bytes as they were sent by

the bus controller

DS28EC20

Increments

Scratchpad

Offset

Controller

TX Reset?

Bus Controller

RX “1”s

Partial

Byte?

PF = 1

If the memory is

write-protected, the

DS28EC20 copies the data byte from

the target address into the scratchpad.

If the memory is in

EPROM mode, the

DS28EC20 stores the bitwise logical

AND of the transmitted byte and the

data byte from the targeted address

into the scratchpad.

DS28EC20 sets (E[4:0]) =

Scratchpad Offset

Note: The PF Flag is set upon power-

on reset. It is cleared only if a com-

plete 16-bit target address is trans-

mitted. Sending less than 16 bits for

the target address sets the PF flag.

DS28EC20 Datasheet(PDF) 13 Page - Analog Devices

DS28EC20 Datasheet(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL