Analog Frequency Multiplier

PL660 and PL663 XO Families

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991

www.phaselink.com

Rev. 3/20/07 Page 2

O s c i l la t o r

A m p l i f i e r

O E

Q

Q B A R

F r e q u e n c y

X 2

X I N

X O U T

L 2 X

F r e q u e n c y

X 4

L 4 X

O n ly r e q u ir e d in x 4 d e s ig n s

R

Figure 2: Block Diagram of AFM XO

Figure 3 shows the period jitter histogram of the 2x Analog Frequency Multiplier at 212.5 MHz, while

Figure 4 shows the very low levels of sub-harmonics that correspond to the exceptional performance (i.e.

low jitter).

Figure 3: Period Jitter Histogram at 212.5MHz

Figure 4: Spectrum Analysis at 212.5MHz

Analog Frequency Multiplier (2x),

Analog Frequency Multiplier (2x),

with 106.25 MHz crystal

with sub-harmonics below –69 dBc

OE LOGIC SELECTION

OUTPUT

OESEL

OE

Output State

0 (Default)

Enabled

0 (Default)

1

Tri-state

0

Tri-state

PECL

1

1 (Default)

Enabled

0

Tri-state

0 (Default)

1 (Default)

Enabled

0 (Default)

Enabled

LVDS or CMOS

1

1

Tri-state

OESEL and OE: Connect to VDD to set to “1”, connect to GND to set to “0”. [The ‘Default’ state is set by internal pull up/down resistor.]