LTC2487CDEPBF datasheet(28/32 Pages) LINER

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LTC2487

2487fa

Usingthe2xspeedmodeoftheLTC2487alterstherejection

characteristics around DC and multiples of fS. The device

bypassestheoffsetcalibrationinordertoincreasetheout-

put rate. The resulting rejection plots are shown in Figures

26 and 27. 1x type frequency rejection can be achieved

using the 2x mode by performing a running average of the

previous two conversion results (see Figure 28).

Output Data Rate

When using its internal oscillator, the LTC2487 produces

upto15samplespersecond(sps)withanotchfrequencyof

60Hz. The actual output data rate depends upon the length

of the sleep and data output cycles which are controlled

by the user and can be made insignificantly short. When

operating with an external conversion clock (FOconnected

to an external oscillator), the LTC2487 output data rate

can be increased. The duration of the conversion cycle is

41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves

as if the internal oscillator is used.

An increase in fEOSC over the nominal 307.2kHz will trans-

late into a proportional increase in the maximum output

data rate (up to a maximum of 100sps). The increase in

output rate leads to degradation in offset, full-scale error

and effective resolution as well as a shift in frequency

rejection. When using the integrated temperature sensor,

the internal oscillator should be used or an external oscil-

lator fEOSC = 307.2kHz maximum.

A change in fEOSC results in a proportional change in the

internal notch position. This leads to reduced differential

mode rejection of line frequencies. The common mode

rejectionoflinefrequenciesremainsunchanged,thusfully

differential input signals with a high degree of symmetry

on both the IN+ and IN– pins will continue to reject line

frequency noise.

An increase in fEOSC also increases the effective dynamic

input and reference current. External RC networks will

continue to have zero differential input current, but the

time required for complete settling (580ns for fEOSC =

307.2kHz) is reduced, proportionally.

Once the external oscillator frequency is increased above

1MHz(amorethan3xincreaseinoutputrate)theeffective-

ness of internal auto calibration circuits begins to degrade.

This results in larger offset errors, full-scale errors, and

decreased resolution, as seen in Figures 29 to 36.

Figure 26. Input Normal Mode Rejection 2x Speed Mode

Figure 27. Input Normal Mode Rejection 2x Speed Mode

applicaTions inForMaTion

INPUT SIGNAL FREQUENCY (fN)

2487 F26

–20

–40

–60

–80

–100

–120

fN 2fN 3fN 4fN 5fN 6fN 7fN 8fN

INPUT SIGNAL FREQUENCY (fN)

2487 F27

–20

–40

–60

–80

–100

–120

250

248

252 254 256 258 260 262 264

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