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LTC3422

3422fa

APPLICATIO S I FOR ATIO

conduct heat away from the LTC3422 and into the copper

plane with as much area as possible. In the event that the

junction temperature gets too high, the peak current limit

will automatically be decreased. If the junction tempera-

ture continues to rise, the LTC3422 will go into thermal

shutdown and all switching will stop until the internal

temperature drops.

VIN > VOUT Operation

The LTC3422 will maintain voltage regulation when the

input voltage is above the output voltage. This is achieved

by terminating the switching of the synchronous P-chan-

nel MOSFET and applying VIN statically on the gate. This

will ensure the volt • seconds of the inductor will reverse

during the time current is flowing to the output. Since this

mode will dissipate more power in the LTC3422, the

maximum output current is limited in order to maintain an

acceptable junction temperature and is given by:

OUT MAX

OUT

()

–

•(

. ) –

()

125

1 5

where TA = ambient temperature.

For example at VIN = 4.5V, VOUT = 3.3V and TA = 85°C, the

maximum output current is 345mA.

Short Circuit

The LTC3422 output disconnect feature allows output

short circuit while maintaining a maximum internally set

current limit. However, the LTC3422 also incorporates

internal features such as current limit foldback and ther-

mal shutdown for protection from an excessive overload

or short circuit. During a prolonged short circuit the

current limit folds back to 0.75A typical should VOUT drop

below approximately 666mV. This 0.75A current limit

remains in effect until VOUT exceedsapproximately800mV,

at which time the steady-state current limit is restored.

Closing the Feedback Loop

The LTC3422 utilizes current mode control with internal

adaptive slope compensation. Current mode control elimi-

nates the 2nd order filter due to the inductor and output

capacitor exhibited in voltage mode controllers, thus

simplifying it to a single pole filter response. The product

of ‘the modulator control to output DC gain’ and ‘the error

amp open-loop gain’ gives the DC gain of the system:

CONTROL OUTPUT

REF

OUT

CONTROL OUTPUT

OUT

≈

••

•

;

2000

The output filter pole is given by:

ƒFILTER POLE

OUT

••

where COUT is the output filter capacitor.

The output filter zero is given by:

ƒFILTER ZERO

ESR

OUT

••

•

where RESR is the capacitor equivalent series resistance.

A troublesome feature of the boost regulator topology is

the right-half plane zero (RHP), given by:

ƒRHPZ

OUT

IL V

2•

•

• •

At heavy loads this gain increase with phase lag can occur

at a relatively low frequency. The loop gain is typically

rolled off before the RHP zero frequency.

The typical error amplifier compensation is shown in

Figure 3. The equations for the loop dynamics are as

follows:

POLE

ZERO

POLE

220 6

≈

••

•

••

•

••

•

which is extremely close to DC

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