21

AMI Semiconductor

www.amis.com

FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC

Data Sheet

10.3.1 Example Programming

Type a value for the crystal resonator frequency in MHz in

the reference crystal box. This frequency provides the

basis for all of the PLL calculations that follow.

Next, click on the PLL A box. A pop-up screen similar to

Figure 14 should appear. Type in a desired output clock

frequency in MHz, set the operating voltage (3.3V or 5V)

and the desired maximum output frequency error.

Pressing calculate solutions generates several possible

divider and VCO-speed combinations.

For a 100MHz output, the VCO should ideally operate at a

higher frequency, and the reference and feedback dividers

should be as small as possible. In this example, highlight

Solution #7. Notice the VCO operates at 200MHz with a

post divider of two to obtain an optimal 50 percent duty

cycle.

Now choose which mux and post divider to use (that is,

choose an output pin for the 100MHz output). Selecting A

places the PostDiv value in Solution #7 into post divider A

and switches mux A to take the output of PLL A.

The PLL screen should disappear, and now the value in

the PLL A box is the new VCO frequency chosen in

Solution #7. Also note that mux A has been switched to

PLL A and the post pivider A has the chosen 100MHz

output displayed.

Repeat the steps for PLL B.

PLL C supports two different output frequencies

depending on the setting of the SEL_CD pin. Both mux C

Figure 14: PLL Screen

and mux D are also affected by the logic level on the

SEL_CD pin, as are the post dividers C and D.

Figure 15:

Post Divider Menu

Click on PLL C1 to open the PLL screen. Set a desired

frequency, however, now choose the post divider B as the

output divider. Notice the post divider box has split in two

(as shown in Figure 15). The post divider B box now

shows that the divider is dependent on the setting of the

SEL_CD pin for as long as mux B is the PLL C output.

Clicking on post divider A reveals a pull-down menu

provided to permit adjustment of the post divider value

independently of the PLL screen. A typical menu is shown

in Figure 15. The range of possible post divider values is

also given in Table 7.

The register settings are shown to the left in the screen

shown in Figure 13. Clicking on a register location

displays a screen shown in Figure 16. Individual bits can

be poked, or the entire register value can be changed.

Figure 16: Register Screen

© 2004 AMI Semiconductor, Inc.

AMI Semiconductor makes no warranty for the use of its products, other than those expressly contained in the company’s standard warranty contained in AMI Semiconductor’s Terms and Conditions. The company

assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to

update the information contained herein. No licenses to patents or other intellectual property of AMI Semiconductor are granted by the company in connection with the sale of AMI Semiconductor products, expressly or

GM