M24256E-FDW6TP datasheet(12/46 Pages) STMICROELECTRONICS

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Instructions

6.1

Write operations on memory array

Following a start condition the bus master sends a device select code with the RW bit (RW) set to 0. The device

acknowledges this, as shown in Figure 6, and waits for two address bytes. The device responds to each address

byte with an acknowledge bit, and then waits for the data byte. See in Section 5.5 Device addressing (Table 5,

Table 6 and Table 7) how to address the memory array.

When the bus master generates a stop condition immediately after a data byte ACK bit (in the “10th bit” time slot),

either at the end of a byte write or a page write, the internal write cycle tW is triggered. A stop condition at any

other time slot does not trigger the internal write cycle.

After the stop condition and the successful completion of an internal write cycle (tW), the device internal address

counter is automatically incremented to point to the next byte after the last modified byte.

During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any

requests.

If the write control input (WC) is driven high, the write instruction is not executed and the accompanying data

bytes are not acknowledged, as shown in Figure 7.

M24256E-F

Instructions

DS12687 - Rev 3

page 12/46

M24256E-FDW6TP Datasheet(PDF) 12 Page - STMicroelectronics