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TDA3504 Datasheet(PDF) 7 Page - NXP Semiconductors |
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TDA3504 Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 12 page ![]() 1996 Jan 09 7 Philips Semiconductors Product specification Video control combination circuit TDA3504 Notes 1. Maximum value 110 mA after warm-up. 2. Values are proportional to the supply voltage. 3. Matrixed according to equation V(G−Y) = −0.51V−(R−Y) − 0.19V−(B−Y). 4. Clipping due to internal signal limitation may occur when the Y input is greater than nominal and maximum contrast and minimum brightness. 5. When V7-18 < 0.4 V during clamping time, the black levels of the inserted RGB signals are clamped on the black levels of the internal RGB signals. When V7-18 > 0.9 V during clamping time, the black levels of the inserted RGB signals are clamped on an internal DC voltage (correct clamping of the external RGB signals is possible only when they are synchronous with the sandcastle pulse). 6. Internal signal limitation is allowed to start at 5.5 V after warm-up time. 7. The sandcastle pulse is compared with three internal thresholds (proportional to VP) and the given levels separate the various pulses. 8. Blanked to ultra-black ( −25%). 9. Pulse duration ≥3.5 µs. Gv1-15; Gv19-14 voltage gain with respect to colour difference inputs (pins 14 and 15) 11 14 17 dB α 1-15; α19-14 frequency response of colour difference paths f=0to2MHz −− 3dB Gv19-10; Gv20-9; Gv1-8 voltage gain with respect to inserted signals 12 14 16 dB α 19-10; α20-9; α1-8 frequency response of inserted signal paths f=0to10MHz −− 3dB ∆t 19, 20, 1 difference in transition times between R, G and B channels − 015 ns td delay time between signal switching and signal insertion −25 − +25 ns ∆G 19, 20, 1 difference in gain between normal and signal insertion mode −− 10 % Sandcastle pulse detector (pin 6) V6 the following amplitudes are required for separating the various pulses horizontal and vertical blanking; notes 7 and 8 2.1 2.5 2.9 V horizontal; note 7 4.1 4.5 5.0 V clamping; notes 7 and 9 7.6 8.0 12.0 V no keying; note 7 −− 1.0 V II input current LOW −− −110 µA td delay of leading edge of clamping pulse − 0.5 −µs SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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