TDA4853 datasheet(26/60 Pages) PHILIPS

26 / 60 page

1999 Jul 13

Philips Semiconductors

Product speciﬁcation

I2C-bus autosync deﬂection controllers for

PC/TV monitors

TDA4853; TDA4854

Notes

1. For duration of vertical blanking pulse see subheading ‘Vertical oscillator [oscillator frequency in application without

adjustment of free-running frequency ffr(V)]’.

2. Continuous blanking at CLBL (pin 16) will be activated, if one of the following conditions is true:

a) No horizontal flyback pulses at HFLB (pin 1) within a line

b) X-ray protection is triggered

c) Voltage at HPLL2 (pin 30) is low during soft start

d) Supply voltage at VCC (pin 10) is low

e) PLL1 unlocked while frequency-locked loop is in search mode.

3. Oscillator frequency is fmin when no sync input signal is present (continuous blanking at pins 16 and 17).

4. Loading of HPLL1 (pin 26) is not allowed.

5. Voltage at HPLL1 (pin 26) is fed to HBUF (pin 27) via a buffer. Disturbances caused by horizontal sync are removed

by an internal sample-and-hold circuit.

6. All vertical and EW adjustments in accordance with note 8, but VSIZE = 80% (register VSIZE = 63 and control

bit VOVSCN = 0).

7. Value of resistor at VREF (pin 23) may not be changed.

8. All vertical and EW adjustments are specified at nominal vertical settings; unless otherwise specified, which means:

a) VSIZE = 100% (register VSIZE = 127 and control bit VOVSCN = 0)

b) VSMOD = 0 (no EHT compensation)

Voff(VCC)

supply voltage level for

deactivation of BDRV, VOUT1,

VOUT2 and HUNLOCK; also

sets register SOFTST

VCC decreasing from

above typical 8.3 V

7.7

8.1

8.5

THRESHOLDS DERIVED FROM HPLL2 VOLTAGE

VHPLL2(blank)(ul)

upper limit voltage for

continuous blanking

−

4.7

−

VHPLL2(bduty)(ul)

upper limit voltage for variation

of BDRV duty cycle

−

3.4

−

VHPLL2(bduty)(ll)

lower limit voltage for variation

of BDRV duty cycle

−

2.8

−

VHPLL2(hduty)(ul)

upper limit voltage for variation

of HDRV duty cycle

−

2.8

−

VHPLL2(hduty)(ll)

lower limit voltage for variation

of HDRV duty cycle

−

1.7

−

VHPLL2(stby)(ll)

lower limit voltage for VOUT1

and VOUT2 to be active via

I2C-bus soft start

−

1.1

−

VHPLL2(stby)(ul)

upper limit voltage for standby

voltage

−

VHPLL2(stby)(ll)

lower limit voltage for VOUT1

and VOUT2 to be active via

external DC current

−

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

TDA4853 Datasheet(PDF) 26 Page - NXP Semiconductors

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