TDA4858 datasheet(21/44 Pages) PHILIPS

21 / 44 page

1997 Oct 27

Philips Semiconductors

Product speciﬁcation

Economy Autosync Deﬂection Controller

(EASDC)

TDA4858

Notes to the characteristics

1. Continuous blanking at CLBL (pin 16) will be activated, if one of the following conditions is true:

a) No horizontal flyback pulses at HFLB (pin 1) within a line

b) X-ray protection is triggered

c) Voltage at HPLL2 (pin 31) is low (for soft start of horizontal drive)

d) Supply voltage at VCC (pin 9) is low

e) PLL1 unlocked while frequency-locked loop is in search mode.

2. Loading of HPLL1 (pin 26) is not allowed.

3. Oscillator frequency is fmin when no sync input signal is present (no continuous blanking at pin 16).

4. Voltage at HPLL1 (pin 26) is fed to HBUF (pin 27) via a buffer. Disturbances caused by horizontal sync are removed

by an internal sample-and-hold circuit.

5. Input resistance at HPOS (pin 30):

6. Full vertical sync range with constant amplitude (fV(min) :fV(max) = 1 : 2.5) can be made usable by choosing an

application with adjustment of free-running frequency.

7. If higher vertical frequencies are required, sync range can be shifted by using a smaller capacitor at VCAP (pin 24).

8. Value of resistor at VREF (pin 23) may not be changed.

9. All vertical and EW adjustments are specified at nominal vertical settings, which means:

∆VAMP = 100% (IVAMP = 135 µA)

∆VSCOR = 0 (pin 19 open-circuit)

∆VPOS centred (pin 17 forced to ground)

d) fH = 70 kHz.

10. The superimposed logarithmic sawtooth at VSCOR (pin 19) tracks with VPOS, but not with VAMP settings.

The superimposed waveform is described by

with ‘d’ being the modulation depth of a sawtooth from

−5⁄

6 to +

⁄

6. A linear sawtooth with the same modulation depth can be recovered in an external long-tailed pair

(see Fig.17).

11. The output signal at EWDRV (pin 11) may consist of parabola + DC shift + trapezium correction. These adjustments

have to be carried out in a correct relationship to each other in order to avoid clipping due to the limited output voltage

range at EWDRV.

12. The superimposed logarithmic parabola at EWTRP (pin 20) tracks with VPOS, but not with VAMP settings

(see Fig.17).

13. If fH tracking is enabled, the amplitude of the complete EWDRV output signal (parabola + DC shift + trapezium) will

be changed proportional to IHREF. The EWDRV low level of 1.2 V remains fixed.

14. First pole of transconductance amplifier is 5 MHz without external capacitor (will become the second pole, if the OTA

operates as an integrator).

15. Open-loop gain is

at f = 0 with no resistive load and CBOP = 4.7 nF [from BOP (pin 3) to GND].

HPOS

------

HPOS

---------------

-------

–

-------------

BOP

BIN

--------------

TDA4858 Datasheet(PDF) 21 Page - NXP Semiconductors

TDA4858 Datasheet(HTML) 21 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL