IR3500MPBF datasheet(21/47 Pages) IRF

21 / 47 page

IR3500

Page 21 of 47

June 12, 2007

START DELAY (TD1)

VCC

ENABLE

1.4V

VOUT

VRRDY

3.92V

SS/DEL

(12V)

NORMAL OPERATION

VDAC

4.0V

VID

SOFT START

TIME (TD2)

VRRDY DELAY

TIME (TD3)

EAOUT

Figure 12 - Start-up sequence of converter without boot voltage

Constant Over-Current Control during Soft Start

The over current limit threshold is set by a resistor connected between OCSET and VDAC. If the IIN pin voltage,

which is proportional to the average current plus VDAC voltage, exceeds the OCSET voltage during soft start, the

constant over-current control is activated. Figure 13 shows the constant over-current control with delay during soft

start. The delay time is set by the ROSC resistor, which sets the number of switching cycles for the delay counter.

The delay is required since over-current conditions can occur as part of normal operation due to inrush current. If an

over-current occurs during soft start (before VRRDY is asserted), the SS/DEL voltage is regulated by the over

current amplifier to limit the output current below the threshold set by OCSET voltage. If the over-current condition

persists after delay time is reached, the fault latch will be set pulling the error amplifier’s output low and inhibiting

switching in the phase ICs. The SS/DEL capacitor will discharge until it reaches 0.2V and the fault latch is reset

allowing a normal soft start to occur. If an over-current condition is again encountered during the soft start cycle, the

constant over-current control actions will repeat and the converter will be in hiccup mode. The delay time is

controlled by a counter which is triggered by clock. The counter values vary with switching frequency per phase in

order to have a similar delay time for different switching frequencies.

Over-Current Hiccup Protection after Soft Start

The over current limit threshold is set by a resistor connected between OCSET and VDAC pins. Figure 13 shows

the constant over-current control with delay after VRRDY is asserted. The delay is required since over-current

conditions can occur as part of normal operation due to load transients or VID transitions.

If the IIN pin voltage, which is proportional to the average current plus VDAC voltage, exceeds the OCSET voltage

after VRRDY is asserted, it will initiate the discharge of the capacitor at SS/DEL. The magnitude of the discharge

current is proportional to the voltage difference between IIN and OCSET and has a maximum nominal value of

55uA. If the over-current condition persists long enough for the SS/DEL capacitor to discharge below the 120mV

offset of the delay comparator, the fault latch will be set pulling the error amplifier’s output low and inhibiting

switching in the phase ICs and de-asserting the VRRDY signal. The output current is not controlled during the delay

time. The SS/DEL capacitor will discharge until it reaches 200 mV and the fault latch is reset allowing a normal soft

start to occur. If an over-current condition is again encountered during the soft start cycle, the over-current action

will repeat and the converter will be in hiccup mode.

IR3500MPBF Datasheet(PDF) 21 Page - International Rectifier

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