MCP9805-BESLASHST datasheet(20/34 Pages) MICROCHIP

20 / 34 page

MCP9805

DS21977B-page 20

5.0

SERIAL COMMUNICATION

5.1

2-Wire SMBus/Standard Mode

I2C™ Protocol-Compatible

Interface

The MCP9805 serial clock input (SCLK) and the

bidirectional serial data line (SDA) form a 2-Wire

bidirectional SMBus/Standard mode I2C compatible

communication port (refer to the Digital Input/Output

Pin Characteristics Table and Serial Interface Timing

Characteristics Table).

The following bus protocol has been defined:

TABLE 5-1:

MCP9805 SERIAL BUS

PROTOCOL DESCRIPTIONS

5.1.1

DATA TRANSFER

Data transfers are initiated by a Start condition

(START), followed by a 7-bit device address and a

read/write bit. An Acknowledge (ACK) from the slave

confirms the reception of each byte. Each access must

be terminated by a Stop condition (STOP).

Repeated communication is initiated after tB-FREE.

This device does not support sequential register

read/write. Each register needs to be addressed using

the Register Pointer.

This device supports the receive protocol. The register

can be specified using the pointer for the initial read

(see Figure 5-4). Each repeated read or receive can

then be followed with a Start condition, followed by an

address byte. The MCP9805 retains the previously

selected register. Therefore, it expects a read from the

previously-specified

(repeated

pointer

specification is not necessary).

5.1.2

MASTER/SLAVE

The bus is controlled by a master device (typically a

microcontroller) that controls the bus access and gener-

ates the Start and Stop conditions. The MCP9805 is a

slave device and does not control other devices in the

bus. Both master and slave devices can operate as

either transmitter or receiver. However, the master

device determines which mode is activated.

5.1.3

START/STOP CONDITION

A high-to-low transition of the SDA line (while SCLK is

high) is the Start condition. All data transfers must be

preceded by a Start condition from the master. If a Start

condition is generated during data transfer, the

MCP9805 resets and accepts the new Start condition.

A low-to-high transition of the SDA line (while SCLK is

high) signifies a Stop condition. If a Stop condition is

introduced during data transmission, the MCP9805

releases the bus. All data transfers are ended by a Stop

condition from the master. However, for continuous data

reception

from

the

previously-specified

pointer

(Register 4-1), a Start condition can be introduced at the

end of data reception. The MCP9805 retains the previ-

ously-set pointer. Therefore, there is no need to repeat

the pointer specification (see Register 5-4).

5.1.4

ADDRESS BYTE

Following the Start condition, the host must transmit an

8-bit address byte to the MCP9805. The address for the

MCP9805 is ‘0011,A2,A1,A0’ in binary, where the A2,

A1 and A0 bits are set externally by connecting the

corresponding pins to VDD ‘1’ or GND ‘0’. The 7-bit

address transmitted in the serial bit stream must match

the selected address for the MCP9805 to respond with

an ACK. Bit 8 in the address byte is a read/write bit.

Setting this bit to ‘1’ commands a read operation, while

‘0’ commands a write operation (see Figure 5-1).

Term

Description

Master

The device that controls the serial bus,

typically a microcontroller.

Slave

The device addressed by the master,

such as the MCP9805.

Transmitter Device sending data to the bus.

Receiver

Device receiving data from the bus.

START

A unique signal from master to initiate

serial interface with a slave.

STOP

A unique signal from the master to

terminate serial interface from a slave.

Read/Write

A read or write to the MCP9805

registers.

ACK

A receiver Acknowledges (ACK) the

reception of each byte by polling the

bus.

NAK

A receiver Not-Acknowledges (NAK) or

releases the bus to show End-of-Data

(EOD).

Busy

Communication is not possible

because the bus is in use.

Not Busy

The bus is in the idle state, both SDA

and SCLK remain high.

Data Valid

SDA must remain stable before SCLK

becomes high in order for a data bit to

be considered valid. During normal

data transfers, SDA only changes state

while SCLK is low.

MCP9805-BE/ST Datasheet(PDF) 20 Page - Microchip Technology

MCP9805-BE/ST Datasheet(HTML) 20 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Datasheet Download

Link URL