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ADAU1361BCPZ-R7 Datasheet(PDF) 67 Page - Analog Devices |
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ADAU1361BCPZ-R7 Datasheet(HTML) 67 Page - Analog Devices |
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67 / 78 page ![]() Data Sheet ADAU1361 CONTROL REGISTERS analog.com Rev. E | 67 of 78 Table 67. Control Port Pad Control 0 Register (Continued) Bits Bit Name Description [5:4] CLCHP[1:0] CLATCH pad pull-up/pull-down configuration. Setting Configuration 00 Pull-up 01 Reserved 10 None (default) 11 Pull-down [3:2] SCLP[1:0] SCL/CCLK pad pull-up/pull-down configuration. Setting Configuration 00 Pull-up 01 Reserved 10 None (default) 11 Pull-down [1:0] SDAP[1:0] SDA/COUT pad pull-up/pull-down configuration. Setting Configuration 00 Pull-up 01 Reserved 10 None (default) 11 Pull-down R41: Control Port Pad Control 1, 16,432 (0x4030) With IOVDD set to 3.3 V, the low and high drive strengths of the SDA/COUT pin are approximately 2.0 mA and 4.0 mA, respectively. With IOVDD set to 1.8 V, the low and high drive strengths are approximately 0.8 mA and 1.7 mA, respectively. The high drive strength mode may be useful for generating a stronger ACK pulse in I2C mode, if needed. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved SDASTR Table 68. Control Port Pad Control 1 Register Bits Bit Name Description 0 SDASTR SDA/COUT pin drive strength. 0 = low (default). 1 = high. R42: Jack Detect Pin Control, 16,433 (0x4031) With IOVDD set to 3.3 V, the low and high drive strengths of the JACKDET/MICIN pin are approximately 2.0 mA and 4.0 mA, respectively. With IOVDD set to 1.8 V, the low and high drive strengths are approximately 0.8 mA and 1.7 mA, respectively. The optional pull-up/ pull-down resistors are nominally 250 kΩ. When enabled, these pull-up/pull-down resistors set the input signals to a defined state when the signal source becomes three-state. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved JDSTR Reserved JDP[1:0] Reserved Table 69. Jack Detect Pin Control Register Bits Bit Name Description 5 JDSTR JACKDET/MICIN pin drive strength. 0 = low (default). 1 = high. |
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