2000 Jan 10

13

Philips Semiconductors

Preliminary specification

Triple high-speed Analog-to-Digital

Converter 110 Msps (ADC)

TDA8752B

The clock output is able to drive an external 10 pF load (for the on-chip ADCs).

The PLL can be used in three different methods:

1. The IC can be used as stand-alone with a sampling frequency of up to 110 MHz for the TDA8752B/8.

2. When an RGB signal is at a pixel frequency exceeding 100 to 200 MHz, it is possible to follow one of the two

possibilities given below:

a) Using one TDA8752B; the sampling rate can be reduced by a factor of two, by sampling the even pixels in the

even frame and the odd pixels in the odd frame. The INV pin is used to toggle between frames.

b) Using two TDA8752Bs the PLL of the master TDA8752B is used to drive both ADC clocks. The PLL of the slave

TDA8752B is disconnected and the CKBO of the master TDA8752B is connected to pin CKEXT of the TDA8752B

master and CKAO to the slave TDA8752B. In this case, on the CKAO pin CKBO will be the output (with bit CKAB

of the master at logic 1)

The master TDA8752B is used to sample the even pixels and the slave TDA8752B for odd pixels, using a 180

°

phase shift between the clocks (CKADCO pins). The master chip and the slave chip have their INV pin LOW,

which guarantees the 180

° shift ADC clock drive. It is then necessary to adjust phase B of the master chip.

Special care should be taken with the quality of the input signal (input setting time).

If CKREFO output signal at the master chip is needed, it is possible to use one of the two phase A values in order

to avoid set-up and hold problems in the SYNCHRO function; e.g. PHASEA = 100000 and PHASEA = 111111.

3. When INV is LOW, CKADCO is equal to CKEXT inverted.

tCKAO

tCKREFO

8 clock periods

FCE470

CKAO

CKREFO

Fig.5 Timing.

if phase A

≥ 01000 or t

if phase A < 01000.

t

phase selector

2

π

-------------------------------

T

CLK(pixel)

2

------------------------

T

CLK(pixel)

2

------------------------