1998 Aug 26

14

Philips Semiconductors

Preliminary specification

12-bit high-speed Analog-to-Digital

Converter (ADC)

TDA8768

Fig.6 Application diagram for differential clock input (PECL-compatible) using a TTL to PECL translator.

If the clock lines are more than 1 inch long they must be matched. In fact, the 27

Ω resistor will be changed

(1) 50

handbook, full pagewidth

MGL474

TDA8768

TRANSLATOR

PECL

CLK

CLK

35

36

D

(1)

270

Ω

270

Ω

100 nF

100 nF

Z0 = 50

Ω

Z0 = 50

Ω

R1

500

Ω

R1

500

Ω

R2

220

Ω

R2

220

Ω

TTL

input

Fig.7

Application diagram for differential clock input (PECL-compatible) using a TTL to PECL translator

and Thevenin parallel terminations.

The value of R1 and R2 must be chosen in order to meet the following relations:

and

(1) 50

Ω matched line (Z

3V

V

CCD

R2

×

R1

R2

+

-----------------------------

=

Z0

R1

R2

×

R1

R2

+

----------------------

=

handbook, full pagewidth

MGL473

TDA8768

TRANSLATOR

PECL

CLK

CLK

35

36

D

VCCD

(1)

R2

120

Ω

R2

120

Ω

100 nF

R1

82

Ω

R1

82

Ω

TTL

input