TDA9144 datasheet(26/44 Pages) PHILIPS

26 / 44 page

1996 Jan 17

Philips Semiconductors

Preliminary speciﬁcation

I2C-bus controlled, alignment-free PAL/NTSC/SECAM

decoder/sync processor with PALplus helper demodulator

TDA9144

Horizontal section

CLP OUTPUT (OPB/CLP MODE); HA OUTPUT (LLC/HA) MODE (BOTH ON PIN 17)

VOH

HIGH level output voltage

4.0

5.5

VOL

LOW level output voltage

−

0.2

0.4

Isink

sink current

−−

Isource

source current

−−

tW(HA)

HA pulse width (32 LLC pulses)

−

4.65

−µs

delay between middle of horizontal

sync pulse and middle of HA

note 4

0.3

0.45

0.6

µs

CLP pulse width (25 LLC pulses)

−

3.65

−µs

delay start CLP pulse to start black

set-up (33 LLC pulses + Y delay)

HD = 1 or MACP = 1; YD3 to

YD0 = 1011; see Fig.5

−

5.35

−µs

delay between middle of horizontal

sync pulse and start of CLP pulse

note 4

3.0

3.2

3.4

µs

σ jitter

ϕ1 in auto mode

−−

5ns

FIRST LOOP (

ϕ1)

∆f

frequency deviation when not locked

−−

1.5

∆VCC

supply voltage dependence

−

Hz/V

fCR

catching range

±625

−−

fHR

holding range

−−±1.0

kHz

static phase shift

−−

0.1

µs/kHz

LLC OUTPUT (PIN 16); LLC/HA MODE

output frequency

440

× f

50 Hz standard

−

6.875

−

MHz

440

× f

60 Hz standard

−

6.923

−

MHz

Vo(p-p)

output amplitude

(peak-to-peak value)

0.25

−−

DC output voltage level

−

2.5

delay between negative edge of LLC

and positive edge of HA pulse

CL = 15 pF

102040ns

Vertical section

VERTICAL OSCILLATOR

ffr

free running frequency

FORF = 1; divider ratio 628

−

FORF = 0; divider ratio 528

−

fLR

frequency locking range

−

divider locking range

488

625

722

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

TDA9144 Datasheet(PDF) 26 Page - NXP Semiconductors

TDA9144 Datasheet(HTML) 26 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL