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DSPIC33FJ12MC02ESS Datasheet(PDF) 218 Page - Microchip Technology |
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DSPIC33FJ12MC02ESS Datasheet(HTML) 218 Page - Microchip Technology |
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218 / 284 page  dsPIC33FJ12MC201/202 DS70265B-page 216 Preliminary © 2007 Microchip Technology Inc. 20.5 JTAG Interface dsPIC33FJ12MC201/202 devices implement a JTAG interface, which supports boundary scan device test- ing, as well as in-circuit programming. Detailed infor- mation on this interface will be provided in future revisions of the document. 20.6 In-Circuit Serial Programming The dsPIC33FJ12MC201/202 devices can be serially programmed while in the end application circuit. This is done with two lines for clock and data and three other lines for power, ground and the programming sequence. Serial programming allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. Serial programming also allows the most recent firmware or a custom firmware to be programmed. Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) document for details about In-Circuit Serial Programming (ICSP). Any of the three pairs of programming clock/data pins can be used: • PGC1/EMUC1 and PGD1/EMUD1 • PGC2/EMUC2 and PGD2/EMUD2 • PGC3/EMUC3 and PGD3/EMUD3 20.7 In-Circuit Debugger When MPLAB® ICD 2 is selected as a debugger, the in- circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the EMUCx (Emulation/Debug Clock) and EMUDx (Emulation/Debug Data) pin functions. Any of the three pairs of debugging clock/data pins can be used: • PGC1/EMUC1 and PGD1/EMUD1 • PGC2/EMUC2 and PGD2/EMUD2 • PGC3/EMUC3 and PGD3/EMUD3 To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS, PGC, PGD and the EMUDx/EMUCx pin pair. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. 20.8 Code Protection and CodeGuard™ Security The dsPIC33FJ12MC201/202 devices offer the intermediate implementation of CodeGuard Security. CodeGuard Security enables multiple parties to securely share resources (memory, interrupts and peripherals) on a single chip. This feature helps protect individual Intellectual Property in collaborative system designs. When coupled with software encryption libraries, CodeGuard Security can be used to securely update Flash even when multiple IPs reside on the single chip. The code protection features vary depending on the actual dsPIC33F implemented. The following sections provide an overview of these features. Secure segment and RAM protection is not implemented in dsPIC33FJ12MC201/202 devices. TABLE 20-3: CODE FLASH SECURITY SEGMENT SIZES FOR 12 KBYTE DEVICES CONFIG BITS BSS<2:0> = x11 0K BSS<2:0> = x10 256 BSS<2:0> = x01 768 BSS<2:0> = x00 1792 Note: Refer to Section 23. “CodeGuard™ Security” (DS70199) of the dsPIC33F Family Reference Manual for further information on usage, configuration and operation of CodeGuard Security. 001FFEh 0001FEh 000200h 000000h VS = 256 IW 0003FEh 000400h 0007FEh 000800h GS = 3840 IW 000FFEh 001000h 001FFEh 0001FEh 000200h 000000h VS = 256 IW 0003FEh 000400h 0007FEh 000800h 000FFEh 001000h GS = 3584 IW BS = 256 IW 001FFEh 0001FEh 000200h 000000h VS = 256 IW 0003FEh 000400h 0007FEh 000800h 000FFEh 001000h GS = 3072 IW BS = 768 IW 001FFEh 0001FEh 000200h 000000h VS = 256 IW 0003FEh 000400h 0007FEh 000800h GS = 2048 IW 000FFEh 001000h BS = 1792 IW |
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