R2J20701NP

REJ03G1459-0300 Rev.3.00 Jun 20, 2007

Page 9 of 27

Description of Operation

Peak Current Control

The control IC operates in a current-programmed control mode, in which the output of the converter is controlled by the

choice of the peak current from the high-side MOS FET. The current from this MOS FET is sensed by an active

current-sensing circuit (ACS), the output current of which is 1/18500 (54 ppm) of the MOS FET current. The ACS

current is then converted to a certain voltage by the external resistor on the CS pin. The CS voltage is fed to the RAMP

pin by an external connection, then compared with the current-control signal which is determined from the error

amplifier output voltage (EO) via an NPN transistor and resistor network.

To start with, the RES pulse from the pulse generator resets a latch, then the high-side MOS FET is turned on. The

latch output (Q bar) is toggled when the voltage on RAMP reaches the level of the current-control signal on EO, the

high-side MOS FET is turned off, and the low-side MOS FET is turned off after a certain dead-time interval. The IC

remains in this state until the arrival of the next RES pulse.

Since current information is used in the control loop, loop compensation design for the converter is simple and easy.

Maximum Duty-Cycle Limitation

If the current-sense comparator output is not toggled 50-ns prior to the arrival of the next RES pulse, an internal

maximum duty pulse is generated and forces toggling of the SR latch. So, the duty cycle of the high-side MOS FET is

limited by the maximum duty period.

The maximum duty period of the high-side MOS FET depends on its switching frequency.

Maximum duty period = 1 – 50 ns

× Fsw

OCP Hiccup Operation

Once the voltage of CS exceeds 1.5 V, OCP hiccup circuit disables switching operation of the IC and MOS FETs.

Internal circuitry also pulls the TRK-SS pin down to SGND. The IC is turned off for a period of 1024 RES pulses; after

this has elapsed, switching operation of the IC is restarted from the soft-start state.

UVLO and On/off Control

When VIN (=Vcin) is below the start-up voltage, that is, is in the UVLO condition, functioning of the IC is disabled.

The oscillator is turned off, both high- and low-side MOS FETs are turned off, and the TRK-SS pin is pulled down.

Furthermore, if the ON/OFF pin is in the low state or left open, functioning of the IC is disabled and both MOS FETs

are turned off.