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PIC18F44J10-E/ML Datasheet(PDF) 220 Page - Microchip Technology |
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PIC18F44J10-E/ML Datasheet(HTML) 220 Page - Microchip Technology |
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220 / 358 page  PIC18F45J10 FAMILY DS39682C-page 218 Preliminary © 2007 Microchip Technology Inc. 17.8 Use of the CCP2 Trigger An A/D conversion can be started by the Special Event Trigger of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving ADRESH:ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user, or an appropriate TACQ time selected before the Special Event Trigger sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), the Special Event Trigger will be ignored by the A/D module, but will still reset the Timer1 counter. TABLE 17-2: REGISTERS ASSOCIATED WITH A/D OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 43 PIR1 PSPIF(1) ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 45 PIE1 PSPIE(1) ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 45 IPR1 PSPIP(1) ADIP RCIP TXIP SSP1IP CCP1IP TMR2IP TMR1IP 45 PIR2 OSCFIF CMIF — — BCL1IF — — CCP2IF 45 PIE2 OSCFIE CMIE — — BCL1IE — — CCP2IE 45 IPR2 OSCFIP CMIP — — BCL1IP — — CCP2IP 45 ADRESH A/D Result Register High Byte 44 ADRESL A/D Result Register Low Byte 44 ADCON0 ADCAL — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 44 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 44 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 44 PORTA — —RA5 — RA3 RA2 RA1 RA0 46 TRISA — — TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 46 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 46 TRISB PORTB Data Direction Control Register 46 LATB PORTB Data Latch Register (Read and Write to Data Latch) 46 PORTE(1) — — — — —RE2 RE1 RE0 46 TRISE(1) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 46 LATE(1) — — — — — PORTE Data Latch Register (Read and Write to Data Latch) 46 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’. |
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