PIC18F44J10-ESLASHML datasheet(321/358 Pages) MICROCHIP

321 / 358 page

Preliminary

DS39682C-page 319

PIC18F45J10 FAMILY

FIGURE 23-12:

EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 0)

TABLE 23-16: EXAMPLE SPI™ MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)

Param

No.

Symbol

Characteristic

Min

Max Units Conditions

TSSL2SCH,

TSSL2SCL

SSx

↓ to SCKx ↓ or SCKx ↑ Input

TCY

—ns

TSCH

SCKx Input High Time

(Slave mode)

Continuous

1.25 TCY + 30

—

71A

Single Byte

—

(Note 1)

TSCL

SCKx Input Low Time

(Slave mode)

Continuous

1.25 TCY + 30

—

72A

Single Byte

—

(Note 1)

TDIV2SCH,

TDIV2SCL

Setup Time of SDIx Data Input to SCKx Edge

100

—

73A

TB2B

Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40

—

(Note 2)

TSCH2DIL,

TSCL2DIL

Hold Time of SDIx Data Input to SCKx Edge

100

—

TDOR

SDOx Data Output Rise Time

—

TDOF

SDOx Data Output Fall Time

—

TSSH2DOZSSx

↑ to SDOx Output High-Impedance

TSCR

SCKx Output Rise Time (Master mode)

—

TSCF

SCKx Output Fall Time (Master mode)

—

TSCH2DOV,

TSCL2DOV

SDOx Data Output Valid after SCKx Edge

—

TSCH2SSH,

TSCL2SSH

SSx

↑ after SCKx Edge

1.5 TCY + 40

—

Note 1:

Requires the use of Parameter #73A.

Only if Parameter #71A and #72A are used.

SSx

SCKx

(CKP = 0)

SCKx

(CKP = 1)

SDOx

SDI

75, 76

SDIx

MSb

LSb

bit 6 - - - - - - 1

MSb In

bit 6 - - - - 1

LSb In

Note:

Refer to Figure 23-3 for load conditions.

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