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PIC18F44J10-E/ML Datasheet(PDF) 328 Page - Microchip Technology |
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PIC18F44J10-E/ML Datasheet(HTML) 328 Page - Microchip Technology |
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328 / 358 page  PIC18F45J10 FAMILY DS39682C-page 326 Preliminary © 2007 Microchip Technology Inc. TABLE 23-24: A/D CONVERTER CHARACTERISTICS: PIC18F24J10/25J10/44J10/45J10 (INDUSTRIAL) FIGURE 23-20: A/D CONVERSION TIMING Param No. Symbol Characteristic Min Typ Max Units Conditions A01 NR Resolution — — 10 bit ΔVREF ≥ 3.0V A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A06 EOFF Offset Error — — <±3 LSb ΔVREF ≥ 3.0V A07 EGN Gain Error — — <±3 LSb ΔVREF ≥ 3.0V A10 — Monotonicity Guaranteed(1) —VSS ≤ VAIN ≤ VREF A20 ΔVREF Reference Voltage Range (VREFH – VREFL) 1.8 3 — — — — V V VDD < 3.0V VDD ≥ 3.0V A21 VREFH Reference Voltage High VSS —VREFH V A22 VREFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V A25 VAIN Analog Input Voltage VREFL —VREFH V A30 ZAIN Recommended Impedance of Analog Voltage Source —— 2.2 k Ω A50 IREF VREF Input Current(2) — — — — 5 150 μA μA During VAIN acquisition. During A/D conversion cycle. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source. 3: Maximum allowed impedance is 8.8 k Ω. This requires higher acquisition time than described in the A/D chapter. 131 130 132 BSF ADCON0, GO Q4 A/D CLK A/D DATA ADRES ADIF GO SAMPLE OLD_DATA SAMPLING STOPPED DONE NEW_DATA (Note 2) 98 7 2 1 0 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. . . . . . . TCY |
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