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PIC18F44J10-E/ML Datasheet(PDF) 160 Page - Microchip Technology

Part # PIC18F44J10-E/ML
Description  28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
PDF  358 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F44J10-E/ML Datasheet(HTML) 160 Page - Microchip Technology

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PIC18F45J10 FAMILY
DS39682C-page 158
Preliminary
© 2007 Microchip Technology Inc.
REGISTER 15-5:
SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN
ACKSTAT
ACKDT
ACKEN(1)
RCEN(1)
PEN(1)
RSEN(1)
SEN(1)
bit 7
bit 0
bit 7
GCEN: General Call Enable bit (Slave mode only)
1
= Enable interrupt when a general call address (0000h) is received in the SSPxSR
0
= General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1
= Acknowledge was not received from slave
0
= Acknowledge was received from slave
bit 5
ACKDT: Acknowledge Data bit (Master Receive mode only)
1
= Not Acknowledge
0
= Acknowledge
Note:
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
bit 4
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(1)
1
= Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0
= Acknowledge sequence Idle
bit 3
RCEN: Receive Enable bit (Master mode only)(1)
1
= Enables Receive mode for I2C
0
= Receive Idle
bit 2
PEN: Stop Condition Enable bit (Master mode only)(1)
1
= Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0
= Stop condition Idle
bit 1
RSEN: Repeated Start Condition Enable bit (Master mode only)(1)
1
= Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by
hardware.
0
= Repeated Start condition Idle
bit 0
SEN: Start Condition Enable/Stretch Enable bit(1)
In Master mode:
1
= Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0
= Start condition Idle
In Slave mode:
1
= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0
= Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode,
these bits may not be set (no spooling) and the SSPxBUF may not be written (or
writes to the SSPxBUF are disabled).
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown



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