PIC18F44J10-ESLASHML datasheet(181/358 Pages) MICROCHIP

181 / 358 page

Preliminary

DS39682C-page 179

PIC18F45J10 FAMILY

15.4.12

ACKNOWLEDGE SEQUENCE

TIMING

An Acknowledge sequence is enabled by setting the

Acknowledge

Sequence

Enable

bit,

ACKEN

(SSPxCON2<4>). When this bit is set, the SCLx pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDAx pin. If the user wishes to

generate an Acknowledge, then the ACKDT bit should

be cleared. If not, the user should set the ACKDT bit

before starting an Acknowledge sequence. The Baud

Rate Generator then counts for one rollover period

(TBRG) and the SCLx pin is deasserted (pulled high).

When the SCLx pin is sampled high (clock arbitration),

the Baud Rate Generator counts for TBRG. The SCLx pin

is then pulled low. Following this, the ACKEN bit is auto-

matically cleared, the Baud Rate Generator is turned off

and the MSSP module then goes into Idle mode

(Figure 15-23).

15.4.12.1

WCOL Status Flag

If the user writes the SSPxBUF when an Acknowledge

sequence is in progress, then WCOL is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

15.4.13

STOP CONDITION TIMING

A Stop bit is asserted on the SDAx pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit,

PEN

(SSPxCON2<2>).

the

end

receive/transmit, the SCLx line is held low after the fall-

ing edge of the ninth clock. When the PEN bit is set, the

master will assert the SDAx line low. When the SDAx

line is sampled low, the Baud Rate Generator is

reloaded and counts down to ‘0’. When the Baud Rate

Generator times out, the SCLx pin will be brought high

and one TBRG (Baud Rate Generator rollover count)

later, the SDAx pin will be deasserted. When the SDAx

pin is sampled high while SCLx is high, the P bit

(SSPxSTAT<4>) is set. A TBRG later, the PEN bit is

cleared and the SSPxIF bit is set (Figure 15-24).

15.4.13.1

WCOL Status Flag

If the user writes the SSPxBUF when a Stop sequence

is in progress, then the WCOL bit is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

FIGURE 15-23:

ACKNOWLEDGE SEQUENCE WAVEFORM

FIGURE 15-24:

STOP CONDITION RECEIVE OR TRANSMIT MODE

Note: TBRG = one Baud Rate Generator period.

SDAx

SCLx

SSPxIF set at

Acknowledge sequence starts here,

write to SSPxCON2

ACKEN automatically cleared

Cleared in

TBRG

the end of receive

ACKEN = 1, ACKDT = 0

SSPxIF

software

SSPxIF set at the end

of Acknowledge sequence

Cleared in

software

ACK

SCLx

SDAx

SDAx asserted low before rising edge of clock

Write to SSPxCON2,

set PEN

Falling edge of

SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG

9th clock

SCLx brought high after TBRG

Note: TBRG = one Baud Rate Generator period.

TBRG

after SDAx sampled high. P bit (SSPxSTAT<4>) is set.

TBRG

to set up Stop condition

ACK

TBRG

PEN bit (SSPxCON2<2>) is cleared by

hardware and the SSPxIF bit is set

PIC18F44J10-E/ML Datasheet(PDF) 181 Page - Microchip Technology

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