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PIC18F4685-I/SP Datasheet(PDF) 321 Page - Microchip Technology |
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PIC18F4685-I/SP Datasheet(HTML) 321 Page - Microchip Technology |
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321 / 484 page ![]() © 2007 Microchip Technology Inc. Preliminary DS39761B-page 319 PIC18F2682/2685/4682/4685 REGISTER 23-59: TXBIE: TRANSMIT BUFFERS INTERRUPT ENABLE REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — — TXB2IE(2) TXB1IE(2) TXB0IE(2) — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-2 TXB2IE:TXB0IE: Transmit Buffer 2-0 Interrupt Enable bit(2) 1 = Transmit buffer interrupt is enabled 0 = Transmit buffer interrupt is disabled bit 1-0 Unimplemented: Read as ‘0’ Note 1: This register is available in Mode 1 and 2 only. 2: TXBnIE in PIE3 register must be set to get an interrupt. REGISTER 23-60: BIE0: BUFFER INTERRUPT ENABLE REGISTER 0(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 B5IE(2) B4IE(2) B3IE(2) B2IE(2) B1IE(2) B0IE(2) RXB1IE(2) RXB0IE(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 B5IE:B0IE: Programmable Transmit/Receive Buffer 5-0 Interrupt Enable bit(2) 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1-0 RXB1IE:RXB0IE: Dedicated Receive Buffer 1-0 Interrupt Enable bit(2) 1 = Interrupt is enabled 0 = Interrupt is disabled Note 1: This register is available in Mode 1 and 2 only. 2: Either TXBnIE or RXBnIE in PIE3 register must be set to get an interrupt. |
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