PIC18F4685-ISLASHSP datasheet(327/484 Pages) MICROCHIP

327 / 484 page

Preliminary

DS39761B-page 325

PIC18F2682/2685/4682/4685

23.3

CAN Modes of Operation

The PIC18F2682/2685/4682/4685 has six main modes

of operation:

• Configuration mode

• Disable mode

• Normal Operation mode

• Listen Only mode

• Loopback mode

• Error Recognition mode

All modes, except Error Recognition, are requested by

setting the REQOP bits (CANCON<7:5>). Error Recog-

nition mode is requested through the RXM bits of the

Receive Buffer register(s). Entry into a mode is

Acknowledged by monitoring the OPMODE bits.

When changing modes, the mode will not actually

change until all pending message transmissions are

complete. Because of this, the user must verify that the

device has actually changed into the requested mode

before further operations are executed.

23.3.1

CONFIGURATION MODE

The CAN module has to be initialized before the

activation. This is only possible if the module is in the

Configuration mode. The Configuration mode is

requested by setting the REQOP2 bit. Only when the

status bit, OPMODE2, has a high level can the initial-

ization be performed. Afterwards, the Configuration

registers, the Acceptance Mask registers and the

Acceptance Filter registers can be written. The module

is activated by setting the REQOP control bits to zero.

The module will protect the user from accidentally

violating the CAN protocol through programming

errors. All registers which control the configuration of

the module can not be modified while the module is on-

line. The CAN module will not be allowed to enter the

Configuration mode while a transmission or reception

is taking place. The Configuration mode serves as a

lock to protect the following registers:

• Configuration Registers

• Functional Mode Selection Registers

• Bit Timing Registers

• Identifier Acceptance Filter Registers

• Identifier Acceptance Mask Registers

• Filter and Mask Control Registers

• Mask Selection Registers

In the Configuration mode, the module will not transmit

or receive. The error counters are cleared and the

interrupt flags remain unchanged. The programmer will

have access to Configuration registers that are access

restricted in other modes.

23.3.2

DISABLE MODE

In Disable mode, the module will not transmit or

receive. The module has the ability to set the WAKIF bit

due to bus activity; however, any pending interrupts will

remain and the error counters will retain their value.

If the REQOP<2:0> bits are set to ‘001’, the module will

enter the module Disable mode. This mode is similar to

disabling other peripheral modules by turning off the

module enables. This causes the module internal clock

to stop unless the module is active (i.e., receiving or

transmitting a message). If the module is active, the

module will wait for 11 recessive bits on the CAN bus,

detect that condition as an Idle bus, then accept the

module disable command. OPMODE<2:0> = 001

indicates whether the module successfully went into the

module Disable mode.

The WAKIF interrupt is the only module interrupt that is

still active in the Disable mode. If the WAKDIS is

cleared and WAKIE is set, the processor will receive an

interrupt whenever the module detects recessive to

dominant transition. On wake-up, the module will auto-

matically be set to the previous mode of operation. For

example, if the module was switched from Normal to

Disable mode on bus activity wake-up, the module will

automatically enter into Normal mode and the first mes-

sage that caused the module to wake-up is lost. The

module will not generate any error frame. Firmware

logic must detect this condition and make sure that

retransmission is requested. If the processor receives

a wake-up interrupt while it is sleeping, more than one

message may get lost. The actual number of messages

lost would depend on the processor oscillator start-up

time and incoming message bit rate.

The I/O pins will revert to normal I/O function when the

module is in the Disable mode.

23.3.3

NORMAL MODE

This

the

standard

operating

mode

the

PIC18F2682/2685/4682/4685 devices. In this mode,

the device actively monitors all bus messages and gen-

erates Acknowledge bits, error frames, etc. This is also

the only mode in which the PIC18F2682/2685/4682/

4685 devices will transmit messages over the CAN

bus.

PIC18F4685-I/SP Datasheet(PDF) 327 Page - Microchip Technology

PIC18F4685-I/SP Datasheet(HTML) 327 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL