PIC18F4685-ISLASHSP datasheet(330/484 Pages) MICROCHIP

330 / 484 page

PIC18F2682/2685/4682/4685

DS39761B-page 328

Preliminary

23.5.4

PROGRAMMABLE AUTO-RTR

BUFFERS

In Mode 1 and 2, any of six programmable transmit/

receive buffers may be programmed to automatically

respond to predefined RTR messages without user

firmware intervention. Automatic RTR handling is

enabled by setting the TXnEN bit in the BSEL0 register

and the RTREN bit in the BnCON register. After this

setup, when an RTR request is received, the TXREQ

bit is automatically set and the current buffer content is

automatically queued for transmission as a RTR

response. As with all transmit buffers, once the TXREQ

bit is set, buffer registers become read-only and any

writes to them will be ignored.

The

following

outlines

the

steps

required

automatically handle RTR messages:

Set buffer to Transmit mode by setting TXnEN

bit to ‘1’ in BSEL0 register.

least

one

acceptance

filter

must

associated with this buffer and preloaded with

expected RTR identifier.

Bit RTREN in BnCON register must be set to ‘1’.

Buffer must be preloaded with the data to be

sent as a RTR response.

Normally, user firmware will keep buffer data registers

up to date. If firmware attempts to update the buffer

while an automatic RTR response is in the process of

transmission, all writes to buffers are ignored.

23.6

CAN Message Transmission

23.6.1

INITIATING TRANSMISSION

For the MCU to have write access to the message

buffer, the TXREQ bit must be clear, indicating that the

message buffer is clear of any pending message to be

transmitted. At a minimum, the SIDH, SIDL and DLC

registers must be loaded. If data bytes are present in

the message, the data registers must also be loaded. If

the message is to use extended identifiers, the

EIDH:EIDL registers must also be loaded and the

EXIDE bit set.

To initiate message transmission, the TXREQ bit must

be set for each buffer to be transmitted. When TXREQ

is set, the TXABT, TXLARB and TXERR bits will be

cleared. To successfully complete the transmission,

there must be at least one node with matching baud

rate on the network.

Setting the TXREQ bit does not initiate a message

transmission; it merely flags a message buffer as ready

for transmission. Transmission will start when the

device detects that the bus is available. The device will

then begin transmission of the highest priority message

that is ready.

When the transmission has completed successfully, the

TXREQ bit will be cleared, the TXBnIF bit will be set and

an interrupt will be generated if the TXBnIE bit is set.

If the message transmission fails, the TXREQ will remain

set, indicating that the message is still pending for trans-

mission and one of the following condition flags will be

set. If the message started to transmit but encountered

an error condition, the TXERR and the IRXIF bits will be

set and an interrupt will be generated. If the message lost

arbitration, the TXLARB bit will be set.

23.6.2

ABORTING TRANSMISSION

The MCU can request to abort a message by clearing

the TXREQ bit associated with the corresponding

message buffer (TXBnCON<3> or BnCON<3>). Set-

ting the ABAT bit (CANCON<4>) will request an abort

of all pending messages. If the message has not yet

started transmission, or if the message started but is

interrupted by loss of arbitration or an error, the abort

will be processed. The abort is indicated when the

module sets the TXABT bit for the corresponding buffer

(TXBnCON<6> or BnCON<6>). If the message has

started to transmit, it will attempt to transmit the current

message fully. If the current message is transmitted

fully and is not lost to arbitration or an error, the TXABT

bit will not be set because the message was trans-

mitted successfully. Likewise, if a message is being

transmitted during an abort request and the message is

lost to arbitration or an error, the message will not be

retransmitted and the TXABT bit will be set, indicating

that the message was successfully aborted.

Once an abort is requested by setting the ABAT or

TXABT bits, it cannot be cleared to cancel the abort

request. Only CAN module hardware or a POR

condition can clear it.

PIC18F4685-I/SP Datasheet(PDF) 330 Page - Microchip Technology

PIC18F4685-I/SP Datasheet(HTML) 330 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL