PIC18F4685-ISLASHSP datasheet(337/484 Pages) MICROCHIP

337 / 484 page

Preliminary

DS39761B-page 335

PIC18F2682/2685/4682/4685

Table 23-3 shows the relation between the clock

generated by the PLL and the frequency error from jitter

(measured jitter-induced error of 2%, Gaussian distribu-

tion, within 3 standard deviations), as a percentage of

the nominal clock frequency.

This is clearly smaller than the expected drift of a crystal

oscillator, typically specified at 100 ppm or 0.01%. If we

add jitter to oscillator drift, we have a total frequency drift

of 0.0132%. The total oscillator frequency errors for

common clock frequencies and bit rates, including both

drift and jitter, are shown in Table 23-4.

TABLE 23-3:

FREQUENCY ERROR FROM JITTER AT VARIOUS PLL GENERATED CLOCK SPEEDS

TABLE 23-4:

TOTAL FREQUENCY ERROR AT VARIOUS PLL GENERATED CLOCK SPEEDS

(100 PPM OSCILLATOR DRIFT, INCLUDING ERROR FROM JITTER)

PLL

Output

Pjitter

Tjitter

Frequency Error at Various Nominal Bit Times (Bit Rates)

μs

(125 Kb/s)

μs

(250 Kb/s)

μs

(500 Kb/s)

μs

(1 Mb/s)

40 MHz

0.5 ns

1 ns

0.00125%

0.00250%

0.005%

0.01%

24 MHz

0.83 ns

1.67 ns

0.00209%

0.00418%

0.008%

0.017%

16 MHz

1.25 ns

2.5 ns

0.00313%

0.00625%

0.013%

0.025%

Nominal PLL Output

Frequency Error at Various Nominal Bit Times (Bit Rates)

μs

(125 Kb/s)

μs

(250 Kb/s)

μs

(500 Kb/s)

μs

(1 Mb/s)

40 MHz

0.01125%

0.01250%

0.015%

0.02%

24 MHz

0.01209%

0.01418%

0.018%

0.027%

16 MHz

0.01313%

0.01625%

0.023%

0.035%

PIC18F4685-I/SP Datasheet(PDF) 337 Page - Microchip Technology

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