PIC18F4685-ISLASHSP datasheet(339/484 Pages) MICROCHIP

339 / 484 page

Preliminary

DS39761B-page 337

PIC18F2682/2685/4682/4685

23.10 Synchronization

To compensate for phase shifts between the oscillator

frequencies of each of the nodes on the bus, each CAN

controller must be able to synchronize to the relevant

signal edge of the incoming signal. When an edge in

the transmitted data is detected, the logic will compare

the location of the edge to the expected time

(Sync_Seg). The circuit will then adjust the values of

Phase Segment 1 and Phase Segment 2 as necessary.

There are two mechanisms used for synchronization.

23.10.1

HARD SYNCHRONIZATION

Hard synchronization is only done when there is a

recessive to dominant edge during a bus Idle condition,

indicating the start of a message. After hard synchroni-

zation, the bit time counters are restarted with

Sync_Seg. Hard synchronization forces the edge

which has occurred to lie within the synchronization

segment of the restarted bit time. Due to the rules of

synchronization, if a hard synchronization occurs, there

will not be a resynchronization within that bit time.

23.10.2

RESYNCHRONIZATION

As a result of resynchronization, Phase Segment 1

may be lengthened or Phase Segment 2 may be short-

ened. The amount of lengthening or shortening of the

phase buffer segments has an upper bound given by

the Synchronization Jump Width (SJW). The value of

the SJW will be added to Phase Segment 1 (see

Figure 23-6) or subtracted from Phase Segment 2 (see

Figure 23-7). The SJW is programmable between 1 TQ

and 4 TQ.

Clocking

information

will

only

derived

from

recessive to dominant transitions. The property, that

only a fixed maximum number of successive bits have

the same value, ensures resynchronization to the bit

stream during a frame.

The phase error of an edge is given by the position of

the edge relative to Sync_Seg, measured in TQ. The

phase error is defined in magnitude of TQ as follows:

• e = 0 if the edge lies within Sync_Seg.

• e > 0 if the edge lies before the sample point.

• e < 0 if the edge lies after the sample point of the

previous bit.

If the magnitude of the phase error is less than, or equal

to, the programmed value of the Synchronization Jump

Width, the effect of a resynchronization is the same as

that of a hard synchronization.

If the magnitude of the phase error is larger than the

Synchronization Jump Width and if the phase error is

positive, then Phase Segment 1 is lengthened by an

amount equal to the Synchronization Jump Width.

If the magnitude of the phase error is larger than the

resynchronization jump width and if the phase error is

negative, then Phase Segment 2 is shortened by an

amount equal to the Synchronization Jump Width.

23.10.3

SYNCHRONIZATION RULES

• Only one synchronization within one bit time is

allowed.

• An edge will be used for synchronization only if

the value detected at the previous sample point

(previously read bus value) differs from the bus

value immediately after the edge.

• All other recessive to dominant edges fulfilling

rules 1 and 2 will be used for resynchronization,

with the exception that a node transmitting a

dominant bit will not perform a resynchronization

as a result of a recessive to dominant edge with a

positive phase error.

FIGURE 23-6:

LENGTHENING A BIT PERIOD (ADDING SJW TO PHASE SEGMENT 1)

Input

Sync

Prop

Segment

Phase

Segment 1

Phase

Segment 2

≤ SJW

Sample Point

Signal

Nominal Bit Length

Actual Bit Length

Bit

Time

Segments

PIC18F4685-I/SP Datasheet(PDF) 339 Page - Microchip Technology

PIC18F4685-I/SP Datasheet(HTML) 339 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL