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PIC18F4685-I/SP Datasheet(PDF) 349 Page - Microchip Technology

Part # PIC18F4685-I/SP
Description  28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
PDF  484 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F4685-I/SP Datasheet(HTML) 349 Page - Microchip Technology

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© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 347
PIC18F2682/2685/4682/4685
REGISTER 24-4:
CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
R/P-1
U-0
U-0
U-0
U-0
R/P-0
R/P-1
U-0
MCLRE
—
—
—
—
LPT1OSC
PBADEN
—
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7
MCLRE: MCLR Pin Enable bit
1
= MCLR pin enabled; RE3 input pin disabled
0
= RE3 input pin enabled; MCLR disabled
bit 6-3
Unimplemented: Read as ‘0’
bit 2
LPT1OSC: Low-Power Timer1 Oscillator Enable bit
1
= Timer1 configured for low-power operation
0
= Timer1 configured for higher power operation
bit 1
PBADEN: PORTB A/D Enable bit
(Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.)
1
= PORTB<4:0> pins are configured as analog input channels on Reset
0
= PORTB<4:0> pins are configured as digital I/O on Reset
bit 0
Unimplemented: Read as ‘0’
REGISTER 24-5:
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1
R/P-0
R/P-0
R/P-0
U-0
R/P-1
U-0
R/P-1
DEBUG
XINST
BBSIZ1
BBSIZ2
—LVP
—STVREN
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7
DEBUG: Background Debugger Enable bit
1
= Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0
= Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
bit 6
XINST: Extended Instruction Set Enable bit
1
= Instruction set extension and Indexed Addressing mode enabled
0
= Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
bit 5
BBSIZ1: Boot Block Size Select Bit 1
11
= 4K words (8 Kbytes) boot block
10
= 4K words (8 Kbytes) boot block
bit 4
BBSIZ2: Boot Block Size Select Bit 0
01
= 2K words (4 Kbytes) boot block
00
= 1K words (2 Kbytes) boot block
bit 3
Unimplemented: Read as ‘0’
bit 2
LVP: Single-Supply ICSP™ Enable bit
1
= Single-Supply ICSP enabled
0
= Single-Supply ICSP disabled
bit 1
Unimplemented: Read as ‘0’
bit 0
STVREN: Stack Full/Underflow Reset Enable bit
1
= Stack full/underflow will cause Reset
0
= Stack full/underflow will not cause Reset



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