 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PIC18F4685-I/SP Datasheet(PDF) 471 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
PIC18F4685-I/SP Datasheet(HTML) 471 Page - Microchip Technology |
|
|
471 / 484 page  © 2007 Microchip Technology Inc. Preliminary DS39761B-page 469 PIC18F2682/2685/4682/4685 Data EEPROM Memory ................................................... 105 Associated Registers ............................................... 109 EEADR and EEADRH Registers ............................. 105 EECON1 and EECON2 Registers ........................... 105 Operation During Code-Protect ............................... 108 Protection Against Spurious Write ........................... 108 Reading .................................................................... 107 Use ........................................................................... 108 Write Verify .............................................................. 107 Writing ...................................................................... 107 Data Memory ..................................................................... 67 Access Bank .............................................................. 69 Bank Select Register (BSR) ....................................... 67 Extended Instruction Set ............................................ 91 General Purpose Register File ................................... 69 Map for PIC18F268X/468X ........................................ 68 Special Function Registers ........................................ 70 DAW ................................................................................. 382 DC and AC Characteristics .............................................. 453 DC Characteristics ........................................................... 428 Power-Down and Supply Current ............................ 420 Supply Voltage ......................................................... 419 DCFSNZ .......................................................................... 383 DECF ............................................................................... 382 DECFSZ ........................................................................... 383 Development Support ...................................................... 413 Device Differences ........................................................... 463 Device Overview .................................................................. 7 Features (table) ............................................................ 9 New Core Features ...................................................... 7 Device Reset Timers .......................................................... 45 Oscillator Start-up Timer (OST) ................................. 45 PLL Lock Time-out ..................................................... 45 Power-up Timer (PWRT) ........................................... 45 Direct Addressing ............................................................... 89 Disable Mode ................................................................... 325 E ECAN Technology ........................................................... 273 Baud Rate Setting .................................................... 333 Bit Time Partitioning ................................................. 333 Bit Timing Configuration Registers .......................... 338 Calculating TQ, Nominal Bit Rate and Nominal Bit Time ............................................. 336 CAN Interrupts ......................................................... 340 Acknowledge ................................................... 342 Bus Activity Wake-up ....................................... 342 Bus-Off ............................................................. 342 Code Bits ......................................................... 341 Error ................................................................. 342 Message Error ................................................. 341 Receive ............................................................ 341 Receiver Bus Passive ...................................... 342 Receiver Overflow ........................................... 342 Receiver Warning ............................................ 342 Transmit ........................................................... 341 Transmitter Bus Passive .................................. 342 Transmitter Warning ........................................ 342 CAN Message Buffers ............................................. 327 Dedicated Receive ........................................... 327 Dedicated Transmit .......................................... 327 Programmable Auto-RTR ................................ 328 Programmable Transmit/Receive .................... 327 CAN Message Transmission ................................... 328 Aborting ........................................................... 328 Initiating ........................................................... 328 Priority ............................................................. 329 CAN Modes of Operation ........................................ 325 CAN Registers ......................................................... 275 Baud Rate ....................................................... 312 Control and Status ........................................... 275 Controller Map ................................................. 320 Dedicated Receive Buffers .............................. 288 Dedicated Transmit Buffers ............................. 282 I/O Control ....................................................... 315 Interrupt ........................................................... 316 Configuration Mode ................................................. 325 Disable Mode ........................................................... 325 Error Detection ........................................................ 339 Acknowledge ................................................... 339 Bit .................................................................... 339 CRC ................................................................. 339 Error States ..................................................... 339 Form ................................................................ 339 Modes and Counters ....................................... 339 Stuff Bit ............................................................ 339 Error Modes State (diagram) ................................... 340 Error Recognition Mode ........................................... 326 Filter-Mask Truth (table) .......................................... 331 Functional Modes .................................................... 326 Mode 0 (Legacy Mode) .................................... 326 Mode 1 (Enhanced Legacy Mode) .................. 326 Mode 2 (Enhanced FIFO Mode) ...................... 327 Information Processing Time (IPT) .......................... 336 Lengthening a Bit Period ......................................... 337 Listen Only Mode ..................................................... 326 Loopback Mode ....................................................... 326 Message Acceptance Filters and Masks ......... 303, 331 Message Acceptance Mask and Filter Operation ................................................ 332 Message Reception ................................................. 330 Enhanced FIFO Mode ..................................... 331 Priority ............................................................. 330 Time-Stamping ................................................ 331 Normal Mode ........................................................... 325 Oscillator Tolerance ................................................. 338 Overview .................................................................. 273 Phase Buffer Segments ........................................... 336 Programmable TX/RX and Auto-RTR Buffers ............................................ 295 Programming Time Segments ................................. 338 Propagation Segment .............................................. 336 Sample Point ........................................................... 336 Shortening a Bit Period ............................................ 338 Synchronization ....................................................... 337 Hard ................................................................. 337 Resynchronization ........................................... 337 Rules ............................................................... 337 Synchronization Segment ........................................ 336 Time Quanta ............................................................ 336 Values for ICODE (table) ......................................... 341 Effect on Standard PIC Instructions ................................. 410 Electrical Characteristics ................................................. 417 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
