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PIC18F4685-I/SP Datasheet(PDF) 472 Page - Microchip Technology |
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PIC18F4685-I/SP Datasheet(HTML) 472 Page - Microchip Technology |
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472 / 484 page  PIC18F2682/2685/4682/4685 DS39761B-page 470 Preliminary © 2007 Microchip Technology Inc. Enhanced Capture/Compare/PWM (ECCP1) .................. 173 Associated Registers ............................................... 186 Capture and Compare Modes .................................. 174 Capture Mode. See Capture (ECCP1 Module). Outputs and Configuration ....................................... 174 Pin Configurations for ECCP1 ................................. 174 PWM Mode. See PWM (ECCP1 Module). Standard PWM Mode ............................................... 174 Timer Resources ...................................................... 174 Enhanced Universal Synchronous Receiver Transmitter (EUSART). See EUSART. Equations A/D Acquisition Time ................................................ 252 A/D Minimum Charging Time ................................... 252 Calculating the Minimum Required A/D Acquisition Time ........................................ 252 Errata ................................................................................... 5 Error Recognition Mode ................................................... 325 EUSART Asynchronous Mode ................................................ 236 Associated Registers, Receive ........................ 239 Associated Registers, Transmit ....................... 237 Auto-Wake-up on Sync Break Character ................................................. 240 Break Character Sequence .............................. 241 Receiver ........................................................... 238 Receiving a Break Character ........................... 241 Setting Up 9-Bit Mode with Address Detect ........................................ 238 Transmitter ....................................................... 236 Baud Rate Generator (BRG) .................................... 231 Associated Registers ....................................... 231 Auto-Baud Rate Detect .................................... 234 Baud Rate Error, Calculating ........................... 231 Baud Rates, Asynchronous Modes .................. 232 High Baud Rate Select (BRGH Bit) .................. 231 Operation in Power-Managed Modes .............. 231 Sampling .......................................................... 231 Synchronous Master Mode ...................................... 242 Associated Registers, Receive ........................ 244 Associated Registers, Transmit ....................... 243 Reception ......................................................... 244 Transmission .................................................... 242 Synchronous Slave Mode ........................................ 245 Associated Registers, Receive ........................ 246 Associated Registers, Transmit ....................... 245 Reception ......................................................... 246 Transmission .................................................... 245 Extended Instruction Set ADDFSR .................................................................. 406 ADDULNK ................................................................ 406 CALLW ..................................................................... 407 MOVSF .................................................................... 407 MOVSS .................................................................... 408 PUSHL ..................................................................... 408 SUBFSR .................................................................. 409 SUBULNK ................................................................ 409 External Clock Input ........................................................... 24 F Fail-Safe Clock Monitor ............................................ 343, 356 Exiting Operation ..................................................... 356 Interrupts in Power-Managed Modes ....................... 357 POR or Wake-up from Sleep ................................... 357 Watchdog Timer (WDT) ........................................... 356 Fast Register Stack ........................................................... 64 Firmware Instructions ...................................................... 363 Flash Program Memory ..................................................... 95 Associated Registers ............................................... 103 Control Registers ....................................................... 96 EECON1 ............................................................ 96 EECON2 ............................................................ 96 TABLAT ............................................................. 96 TABLAT (Table Latch) Register ........................ 98 TBLPTR ............................................................. 96 TBLPTR (Table Pointer) Register ...................... 98 Erase Sequence ...................................................... 100 Erasing .................................................................... 100 Operation During Code-Protect ............................... 103 Reading ..................................................................... 99 Table Pointer Boundaries Based on Operation ....................... 98 Table Pointer Boundaries .......................................... 98 Table Pointer Operations (table) ................................ 98 Table Reads and Table Writes .................................. 95 Write Sequence ....................................................... 101 Write Verify .............................................................. 103 Writing ..................................................................... 101 Protection Against Spurious Writes ................. 103 Unexpected Termination ................................. 103 FSCM. See Fail-Safe Clock Monitor. G GOTO .............................................................................. 384 H Hardware Multiplier .......................................................... 111 Introduction .............................................................. 111 Operation ................................................................. 111 Performance Comparison ........................................ 111 High/Low-Voltage Detect ................................................. 267 Associated Registers ............................................... 271 Characteristics ......................................................... 432 Current Consumption ............................................... 269 Effects of a Reset .................................................... 271 Operation ................................................................. 268 Operation During Sleep ........................................... 271 Setup ....................................................................... 269 Start-up Time ........................................................... 269 Typical Application ................................................... 270 HLVD. See High/Low-Voltage Detect. I I/O Ports ........................................................................... 129 I2C Mode (MSSP) Acknowledge Sequence Timing .............................. 220 Baud Rate Generator .............................................. 213 Bus Collision During a Repeated Start Condition .................. 224 During a Start Condition .................................. 222 During a Stop Condition .................................. 225 Clock Arbitration ...................................................... 214 Clock Stretching ....................................................... 206 10-Bit Slave Receive Mode (SEN = 1) ............ 206 10-Bit Slave Transmit Mode ............................ 206 7-Bit Slave Receive Mode (SEN = 1) .............. 206 7-Bit Slave Transmit Mode .............................. 206 Clock Synchronization and the CKP Bit ................... 207 Effect of a Reset ...................................................... 221 General Call Address Support ................................. 210 I2C Clock Rate w/BRG ............................................. 213 |
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