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PIC18F4685-I/SP Datasheet(PDF) 187 Page - Microchip Technology |
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PIC18F4685-I/SP Datasheet(HTML) 187 Page - Microchip Technology |
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187 / 484 page ![]() © 2007 Microchip Technology Inc. Preliminary DS39761B-page 185 PIC18F2682/2685/4682/4685 16.4.9 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCP1 module for PWM operation: 1. Configure the PWM pins, P1A and P1B (and P1C and P1D, if used), as inputs by setting the corresponding TRIS bits. 2. Set the PWM period by loading the PR2 register. 3. Configure the ECCP1 module for the desired PWM mode and configuration by loading the ECCP1CON register with the appropriate values: • Select one of the available output configurations and direction with the EPWM1M1:EPWM1M0 bits. • Select the polarities of the PWM output signals with the ECCP1M3:ECCP1M0 bits. 4. Set the PWM duty cycle by loading the ECCPR1L register and ECCP1CON<5:4> bits. 5. For Half-Bridge Output mode, set the dead- band delay by loading ECCP1DEL<6:0> with the appropriate value. 6. If auto-shutdown operation is required, load the ECCP1AS register: • Select the auto-shutdown sources using the ECCPAS2:ECCPAS0 bits. • Select the shutdown states of the PWM output pins using PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits. • Set the ECCPASE bit (ECCP1AS<7>). • Configure the comparators using the CMCON register. • Configure the comparator inputs as analog inputs. 7. If auto-restart operation is required, set the PRSEN bit (ECCP1DEL<7>). 8. Configure and start TMR2: • Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit (PIR1<1>). • Set the TMR2 prescale value by loading the T2CKPS bits (T2CON<1:0>). • Enable Timer2 by setting the TMR2ON bit (T2CON<2>). 9. Enable PWM outputs after a new PWM cycle has started: • Wait until TMRx overflows (TMRxIF bit is set). • Enable the ECCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). 16.4.10 EFFECTS OF A RESET Both Power-on Reset and subsequent Resets will force all ports to Input mode and the ECCP1 registers to their Reset states. This forces the Enhanced CCP1 module to reset to a state compatible with the standard CCP1 module. |
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