PIC16F946-ESLASHMLQTP datasheet(198/330 Pages) MICROCHIP

198 / 330 page

PIC16F913/914/916/917/946

DS41250F-page 196

14.2

Operation

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPCON<5:0> and SSPSTAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Data Input Sample Phase (middle or end of data

output time)

• Clock Edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

The SSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR

until the received data is ready. Once the eight bits of

data have been received, that byte is moved to the

SSPBUF register. Then, the Buffer Full Status bit BF of

the SSPSTAT register, and the interrupt flag bit SSPIF,

are set. Any write to the SSPBUF register during

transmission/reception of data will be ignored and the

Write Collision Detect bit, WCOL of the SSPCON

WCOL bit so that it can be determined if the following

write(s)

the

SSPBUF

completed

successfully.

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data to transfer is written to the SSPBUF. Buffer

Full bit BF of the SSPSTAT register indicates when

SSPBUF has been loaded with the received data

(transmission is complete). When the SSPBUF is read,

the BF bit is cleared. This data may be irrelevant if the

SPI is only a transmitter. Generally, the SSP interrupt is

used to determine when the transmission/reception

has completed. The SSPBUF must be read and/or

written. If the interrupt method is not going to be used,

then software polling can be done to ensure that a write

collision does not occur. Example 14-1 shows the

loading of the SSPBUF (SSPSR) for data transmission.

The SSPSR is not directly readable or writable and can

only be accessed by addressing the SSPBUF register.

Additionally, the SSP STATUS register (SSPSTAT)

indicates the various status conditions.

EXAMPLE 14-1:

LOADING THE SSPBUF (SSPSR) REGISTER

BANKSEL

SSPSTAT

;

LOOP

BTFSS

SSPSTAT, BF

;Has data been received(transmit complete)?

GOTO

LOOP

;No

BANKSEL

SSPBUF

;

MOVF

SSPBUF, W

;WREG reg = contents of SSPBUF

MOVWF

RXDATA

;Save in user RAM, if data is meaningful

MOVF

TXDATA, W

;W reg = contents of TXDATA

MOVWF

SSPBUF

;New data to xmit

PIC16F946-E/MLQTP Datasheet(PDF) 198 Page - Microchip Technology

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