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PIC16F946-E/MLQTP Datasheet(PDF) 196 Page - Microchip Technology

Part # PIC16F946-E/MLQTP
Description  28/40/44/64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology
PDF  330 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16F946-E/MLQTP Datasheet(HTML) 196 Page - Microchip Technology

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PIC16F913/914/916/917/946
DS41250F-page 194
© 2007 Microchip Technology Inc.
REGISTER 14-1:
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
PS
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SMP: SPI Data Input Sample Phase bit
SPI Master mode:
1
= Input data sampled at end of data output time
0
= Input data sampled at middle of data output time (Microwire)
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
I2C™ mode:
This bit must be maintained clear
bit 6
CKE: SPI Clock Edge Select bit
SPI mode, CKP = 0:
1
= Data stable on rising edge of SCK (Microwire alternate)
0
= Data stable on falling edge of SCK
SPI mode, CKP = 1:
1
= Data stable on falling edge of SCK (Microwire default)
0
= Data stable on rising edge of SCK
I2C mode:
This bit must be maintained clear
bit 5
D/A: DATA/ADDRESS bit (I2C mode only)
1
= Indicates that the last byte received or transmitted was data
0
= Indicates that the last byte received or transmitted was address
bit 4
P: Stop bit (I2C mode only)
This bit is cleared when the SSP module is disabled, or when the Start bit is detected last.
SSPEN is cleared.
1
= Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0
= Stop bit was not detected last
bit 3
S: Start bit (I2C mode only)
This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last.
SSPEN is cleared.
1
= Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0
= Start bit was not detected last
bit 2
R/W: READ/WRITE bit Information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match
to the next Start bit, Stop bit or ACK bit.
1
= Read
0
= Write
bit 1
UA: Update Address bit (10-bit I2C mode only)
1
= Indicates that the user needs to update the address in the SSPADD register
0
= Address does not need to be updated
bit 0
BF: Buffer Full Status bit
Receive (SPI and I2C modes):
1
= Receive complete, SSPBUF is full
0
= Receive not complete, SSPBUF is empty
Transmit (I2C mode only):
1
= Transmit in progress, SSPBUF is full
0
= Transmit complete, SSPBUF is empty



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