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PIC16F946-E/MLQTP Datasheet(PDF) 203 Page - Microchip Technology |
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PIC16F946-E/MLQTP Datasheet(HTML) 203 Page - Microchip Technology |
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203 / 330 page  © 2007 Microchip Technology Inc. DS41250F-page 201 PIC16F913/914/916/917/946 14.8 Sleep Operation In Master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from Sleep. After the device returns to Normal mode, the module will continue to transmit/receive data. In Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the SSP interrupt flag bit will be set and if enabled, will wake the device from Sleep. 14.9 Effects of a Reset A Reset disables the SSP module and terminates the current transfer. 14.10 Bus Mode Compatibility Table 14-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. TABLE 14-1: SPI BUS MODES There is also a SMP bit which controls when the data is sampled. TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Standard SPI Mode Terminology Control Bits State CKP CKE 0 , 00 1 0 , 10 0 1 , 01 1 1 , 11 0 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011 LCDSE0 SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 0000 0000 LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 0000 0000 PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode. |
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