PIC16F946-ESLASHMLQTP datasheet(236/330 Pages) MICROCHIP

236 / 330 page

PIC16F913/914/916/917/946

DS41250F-page 234

16.4

Watchdog Timer (WDT)

For PIC16F91X/946, the WDT has been modified from

previous PIC16F devices. The new WDT is code and

functionally compatible with previous PIC16F WDT

modules and adds a 16-bit prescaler to the WDT. This

allows the user to have a scaled value for the WDT and

TMR0 at the same time. In addition, the WDT time-out

value can be extended to 268 seconds. WDT is cleared

under certain conditions described in Table 16-7.

16.4.1

WDT OSCILLATOR

The WDT derives its time base from the 31 kHz

LFINTOSC. The LTS bit does not reflect that the

LFINTOSC is enabled.

The value of WDTCON is ‘---0 1000’ on all Resets.

This gives a nominal time base of 16 ms, which is

compatible with the time base generated with previous

PIC16F microcontroller versions.

A new prescaler has been added to the path between

the INTOSC and the multiplexers used to select the

path for the WDT. This prescaler is 16 bits and can be

programmed to divide the INTOSC by 32 to 65536,

giving the WDT a nominal range of 1 ms to 268s.

16.4.2

WDT CONTROL

The WDTE bit is located in the Configuration Word

When the WDTE bit in the Configuration Word register

is set, the SWDTEN bit of the WDTCON register has no

effect. If WDTE is clear, then the SWDTEN bit can be

used to enable and disable the WDT. Setting the bit will

enable it and clearing the bit will disable it.

The PSA and PS<2:0> bits of the OPTION register

have the same function as in previous versions of the

PIC16F family of microcontrollers. See Section 5.0

“Timer0 Module” for more information.

FIGURE 16-9:

WATCHDOG TIMER BLOCK DIAGRAM

Note:

When the Oscillator Start-up Timer (OST)

is invoked, the WDT is held in Reset,

because the WDT Ripple Counter is used

by the OST to perform the oscillator delay

count. When the OST count has expired,

the WDT will begin counting (if enabled).

TABLE 16-7:

WDT STATUS

Conditions

WDT

WDTE = 0

Cleared

CLRWDT

Command

Oscillator Fail Detected

Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP

Cleared until the end of OST

31 kHz

PSA

16-bit WDT Prescaler

From TMR0 Clock Source

Prescaler(1)

PS<2:0>

PSA

WDT Time-out

To TMR0

WDTPS<3:0>

WDTE from Configuration Word register

SWDTEN from WDTCON

LFINTOSC Clock

Note 1: This is the shared Timer0/WDT prescaler. See Section 5.4 “Prescaler” for more information.

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