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AD8691AUJZ-R2 Datasheet(PDF) 12 Page - Analog Devices |
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AD8691AUJZ-R2 Datasheet(HTML) 12 Page - Analog Devices |
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12 / 16 page ![]() AD8691/AD8692/AD8694 Data Sheet Rev. F | Page 12 of 16 COMPLIANT TO JEDEC STANDARDS MO-203-AA 1.00 0.90 0.70 0.46 0.36 0.26 2.20 2.00 1.80 2.40 2.10 1.80 1.35 1.25 1.15 0.10 MAX 1.10 0.80 0.40 0.10 0.22 0.08 3 1 2 4 5 0.65 BSC COPLANARITY 0.10 SEATING PLANE 0.30 0.15 Figure 34. 5-Lead Thin Shrink Small Outline Package [SC70] (KS-5) Dimensions shown in millimeters *COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. 1.60 BSC 2.80 BSC 1.90 BSC 0.95 BSC 0.20 0.08 0.60 0.45 0.30 8° 4° 0° 0.50 0.30 0.10 MAX *1.00 MAX *0.90 MAX 0.70 MIN 2.90 BSC 5 4 1 2 3 SEATING PLANE Figure 35. 5-Lead Thin Small Outline Transistor Package [TSOT] (UJ-5) Dimensions shown in millimeters |
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