DSPIC33FJ32GP202-ESLASHSP datasheet(101/252 Pages) MICROCHIP

101 / 252 page

Preliminary

DS70290A-page 99

dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304

8.0

POWER-SAVING FEATURES

The

dsPIC33FJ32GP202/204

and

dsPIC33FJ16GP304 devices provide the ability to

manage power consumption by selectively managing

clocking to the CPU and the peripherals. In general, a

lower clock frequency and a reduction in the number of

circuits being clocked constitutes lower consumed

power.

dsPIC33FJ32GP202/204

and

dsPIC33FJ16GP304 devices can manage power con-

sumption in four different ways:

• Clock frequency

• Instruction-based Sleep and Idle modes

• Software-controlled Doze mode

• Selective peripheral control in software

Combinations of these methods can be used to selec-

tively tailor an application’s power consumption while

still maintaining critical application features, such as

timing-sensitive communications.

8.1

Clock Frequency and Clock

Switching

dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304

devices allow a wide range of clock frequencies to be

selected under application control. If the system clock

configuration is not locked, users can choose

low-power or high-precision oscillators by simply

changing the NOSC bits (OSCCON<10:8>). The pro-

cess of changing a system clock during operation, as

well as limitations to the process, are discussed in

more detail in Section 7.0 “Oscillator Configura-

tion”.

8.2

Instruction-Based Power-Saving

Modes

dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304

devices have two special power-saving modes that are

entered through the execution of a special PWRSAV

instruction. Sleep mode stops clock operation and halts

all code execution. Idle mode halts the CPU and code

execution, but allows peripheral modules to continue

operation. The Assembler syntax of the PWRSAV

instruction is shown in Example 8-1.

Sleep and Idle modes can be exited as a result of an

enabled interrupt, WDT time-out or a device Reset. When

the device exits these modes, it is said to wake-up.

8.2.1

SLEEP MODE

The following occur in Sleep mode:

• The system clock source is shut down. If an

on-chip oscillator is used, it is turned off.

• The device current consumption is reduced to a

minimum, provided that no I/O pin is sourcing

current.

• The Fail-Safe Clock Monitor does not operate,

since the system clock source is disabled.

• The LPRC clock continues to run if the WDT is

enabled.

• The WDT, if enabled, is automatically cleared

prior to entering Sleep mode.

• Some device features or peripherals may continue

to operate. This includes items such as the input

change notification on the I/O ports, or peripherals

that use an external clock input.

• Any peripheral that requires the system clock

source for its operation is disabled.

The device will wake-up from Sleep mode on any of the

these events:

• Any interrupt source that is individually enabled

• Any form of device Reset

• A WDT time-out

On wake-up from Sleep mode, the processor restarts

with the same clock source that was active when Sleep

mode was entered.

EXAMPLE 8-1:

PWRSAV INSTRUCTION SYNTAX

Note:

This data sheet summarizes the features

the

dsPIC33FJ32GP202/204

and

dsPIC33FJ16GP304 devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC33F

Family Reference Manual”.

Note:

SLEEP_MODE and IDLE_MODE are

constants defined in the assembler

include file for the selected device.

PWRSAV #SLEEP_MODE

; Put the device into SLEEP mode

PWRSAV #IDLE_MODE

; Put the device into IDLE mode

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