DSPIC33FJ32GP202-ESLASHSP datasheet(108/252 Pages) MICROCHIP

108 / 252 page

dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304

DS70290A-page 106

Preliminary

9.4.3.3

Mapping

The control schema of peripheral select pins is not lim-

ited to a small range of fixed peripheral configurations.

There are no mutual or hardware-enforced lockouts

between any of the peripheral mapping SFRs. Literally

any combination of peripheral mappings across any or

all of the RPn pins is possible. This includes both

many-to-one and one-to-many mappings of peripheral

inputs and outputs to pins.

While such mappings may be technically possible from

a configuration point of view, they may not be support-

able electrically.

9.4.4

CONTROLLING CONFIGURATION

CHANGES

Because peripheral remapping can be changed during

run time, some restrictions on peripheral remapping

are needed to prevent accidental configuration

changes. dsPIC33F devices include three features to

prevent alterations to the peripheral map:

• Control register lock sequence

• Continuous state monitoring

• Configuration bit pin select lock

9.4.4.1

Control Register Lock

Under normal operation, writes to the RPINRx and

RPORx registers are not allowed. Attempted writes

appear to execute normally, but the contents of the reg-

isters remain unchanged. To change these registers,

they must be unlocked in hardware. The register lock is

controlled by the IOLOCK bit (OSCCON<6>). Setting

IOLOCK prevents writes to the control registers; clear-

ing IOLOCK allows writes.

To set or clear IOLOCK, a specific command sequence

must be executed:

Write 46h to OSCCON<7:0>.

Write 57h to OSCCON<7:0>.

Clear (or set) IOLOCK as a single operation.

Unlike the similar sequence with the oscillator’s LOCK

bit, IOLOCK remains in one state until changed. This

allows all of the peripheral pin selects to be configured

with a single unlock sequence followed by an update to

all control registers, then locked with a second lock

sequence.

9.4.4.2

Continuous State Monitoring

In addition to being protected from direct writes, the

contents of the RPINRx and RPORx registers are

constantly monitored in hardware by shadow registers.

If an unexpected change in any of the registers occurs

(such as cell disturbances caused by ESD or other

external events), a configuration mismatch Reset will

be triggered.

9.4.4.3

Configuration Bit Pin Select Lock

As an additional level of safety, the device can be con-

figured to prevent more than one write session to the

RPINRx and RPORx registers. The IOL1WAY

(FOSC<IOL1WAY>) configuration bit blocks the

IOLOCK bit from being cleared after it has been set

once.

In the default (unprogrammed) state, IOL1WAY is set,

restricting users to one write session. Programming

IOL1WAY allows user applications unlimited access

(with the proper use of the unlock sequence) to the

peripheral pin select registers.

9.4.5

CONSIDERATIONS FOR

PERIPHERAL PIN SELECTION

The ability to control peripheral pin selection introduces

several considerations into application design, includ-

ing several common peripherals that are only available

as remappable peripherals.

9.4.5.1

Configuration

The peripheral pin selects are not available on default

pins in the device’s default (Reset) state. More specifi-

cally, since all RPINRx and RPORx registers reset to

0000h, this means all peripheral pin select inputs are

tied to RP0, while all peripheral pin select outputs are

disconnected. This means that before any other appli-

cation code is executed, the user application must ini-

tialize the

device

with the proper

peripheral

configuration.

Since the IOLOCK bit resets in the unlocked state, it is

not necessary to execute the unlock sequence after the

device has come out of Reset. For the sake of applica-

tion safety, however, it is always a good idea to set

IOLOCK and lock the configuration after writing to the

control registers.

Because the unlock sequence is timing-critical, it must

be executed as an assembly-language routine, in the

same

manner

changes

the

oscillator

configuration. If the bulk of the application is written in

C or another high-level language, the unlock sequence

should be performed by writing inline assembly.

Note:

MPLAB® C30 provides built-in C language

functions for unlocking the OSCCON

__builtin_write_OSCCONL(value)

__builtin_write_OSCCONH(value)

See MPLAB IDE Help for more

information.

DSPIC33FJ32GP202-E/SP Datasheet(PDF) 108 Page - Microchip Technology

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