DSPIC33FJ32GP202-ESLASHSP datasheet(154/252 Pages) MICROCHIP

154 / 252 page

dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304

DS70290A-page 152

Preliminary

15.11 Slope Control

The I2C standard requires slope control on the SDAx

and SCLx signals for Fast mode (400 kHz). The control

bit, DISSLW, enables the user application to disable

slew rate control if desired. It is necessary to disable

the slew rate control for 1 MHz mode.

15.12 Clock Arbitration

Clock arbitration occurs when the master deasserts the

SCLx pin (SCLx allowed to float high) during any

receive, transmit or Restart/Stop condition. When the

SCLx pin is allowed to float high, the Baud Rate Gen-

erator (BRG) is suspended from counting until the

SCLx pin is actually sampled high. When the SCLx pin

is sampled high, the BRG is reloaded with the contents

of I2CxBRG and begins counting. This process

ensures that the SCLx high time will always be at least

one BRG rollover count in the event that the clock is

held low by an external device.

15.13 Multi-Master Communication, Bus

Collision and Bus Arbitration

Multi-Master mode support is achieved by bus

arbitration. When the master outputs address/data bits

onto the SDAx pin, arbitration takes place when the

master outputs a ‘1’ on SDAx by letting SDAx float high

while another master asserts a ‘0’. When the SCLx pin

floats high, data should be stable. If the expected data

on SDAx is a ‘1’ and the data sampled on the

SDAx pin = 0, then a bus collision has taken place. The

master will set the I2C master events interrupt flag and

reset the master portion of the I2C port to its Idle state.

15.14 Peripheral Pin Select Limitations

The I2C module has limited peripheral pin select func-

tionality. When the ACTI2C bit in the FPOR configura-

tion register is set to ‘1‘, the module uses the SDAx/

SCLx pins. If the ALTI2C bit is ‘0‘

, the module uses the

ASDAx/ASCLx pins.

DSPIC33FJ32GP202-E/SP Datasheet(PDF) 154 Page - Microchip Technology