DSPIC33FJ32GP202-ESLASHSP datasheet(163/252 Pages) MICROCHIP

163 / 252 page

Preliminary

DS70290A-page 161

dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304

16.2

Transmitting in 8-bit Data Mode

Set up the UART:

Write appropriate values for data, parity and

Stop bits.

Write appropriate baud rate value to the

BRGx register.

Set up transmit and receive interrupt enable

and priority bits.

Enable the UART.

Set the UTXEN bit (causes a transmit interrupt).

Write data byte to lower byte of UxTXREG word.

The value will be immediately transferred to the

Transmit Shift Register (TSR) and the serial bit

stream will start shifting out with the next rising

edge of the baud clock.

Alternately, the data byte can be transferred

while UTXEN = 0, and the user application can

set UTXEN. This causes the serial bit stream to

begin immediately, because the baud clock

starts from a cleared state.

A transmit interrupt will be generated as per

interrupt control bits, UTXISEL<1:0>.

16.3

Transmitting in 9-bit Data Mode

Set up the UART (as described in Section 16.2

“Transmitting in 8-bit Data Mode”).

Enable the UART.

Set the UTXEN bit (causes a transmit interrupt).

Write UxTXREG as a 16-bit value only.

A word write to UxTXREG triggers the transfer

of the 9-bit data to the TSR. The serial bit stream

will start shifting out with the first rising edge of

the baud clock.

A transmit interrupt will be generated as per the

setting of control bits, UTXISEL<1:0>.

16.4

Break and Sync Transmit

Sequence

The following sequence will send a message frame

header made up of a Break, followed by an auto-baud

Sync byte.

Configure the UART for the desired mode.

Set UTXEN and UTXBRK, which sets up the

Break character.

Load the UxTXREG register with a dummy

character to initiate transmission (value is

ignored).

Write 0x55 to UxTXREG, which loads the Sync

character into the transmit FIFO. After the Break

has been sent, the UTXBRK bit is reset by hard-

ware. The Sync character now transmits.

16.5

Receiving in 8-bit or 9-bit Data

Mode

Set up the UART (as described in Section 16.2

“Transmitting in 8-bit Data Mode”).

Enable the UART. A receive interrupt will be

generated when one or more data characters

have been received as per interrupt control bits,

URXISEL<1:0>.

Read the OERR bit to determine if an overrun

error has occurred. The OERR bit must be reset

in software.

Read UxRXREG.

The act of reading the UxRXREG character will move

the next character to the top of the receive FIFO,

including a new set of PERR and FERR values.

16.6

Flow Control Using UxCTS and

UxRTS Pins

UARTx Clear to Send (UxCTS) and Request to Send

(UxRTS) are the two hardware controlled active-low

pins associated with the UART module. The UEN<1:0>

bits in the UxMODE register configure these pins.

These two pins allow the UART to operate in Simplex

and Flow Control modes. They are implemented to

control the transmission and the reception between the

Data Terminal Equipment (DTE).

16.7

Infrared Support

The UART module provides two types of infrared UART

support:

• IrDA clock output to support external IrDA

encoder and decoder device (legacy module

support)

• Full implementation of the IrDA encoder and

decoder.

DSPIC33FJ32GP202-E/SP Datasheet(PDF) 163 Page - Microchip Technology

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