PIC24HJ12GP201ESLASHML datasheet(168/234 Pages) MICROCHIP

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PIC24HJ12GP201/202

DS70282B-page 166

Preliminary

18.2

On-Chip Voltage Regulator

All of the PIC24HJ12GP201/202 devices power their

core digital logic at a nominal 2.5V. This can create a

conflict for designs that are required to operate at a

higher typical voltage, such as 3.3V. To simplify system

design, all devices in the PIC24HJ12GP201/202 family

incorporate an on-chip regulator that allows the device

to run its core logic from VDD.

The regulator provides power to the core from the other

VDD pins. When the regulator is enabled, a low-ESR

(less than 5 ohms) capacitor (such as tantalum or

ceramic) must be connected to the VDDCORE/VCAP pin

(Figure 18-1). This helps to maintain the stability of the

regulator. The recommended value for the filter capac-

itor is provided in Table 21-13 located in Section 21.1

“DC Characteristics”.

On a POR

, it takes approximately 20 μs for the on-chip

voltage regulator to generate an output voltage. During

this time, designated as TSTARTUP, code execution is

disabled. TSTARTUP is applied every time the device

resumes operation after any power-down.

FIGURE 18-1:

CONNECTIONS FOR THE

ON-CHIP VOLTAGE

REGULATOR(1)

18.3

BOR: Brown-Out Reset

The Brown-out Reset (BOR) module is based on an

internal voltage reference circuit that monitors the reg-

ulated voltage VDDCORE. The main purpose of the BOR

module is to generate a device Reset when a brown-

out condition occurs. Brown-out conditions are gener-

ally caused by glitches on the AC mains (for example,

missing portions of the AC cycle waveform due to bad

power transmission lines, or voltage sags due to exces-

sive current draw when a large inductive load is turned

on).

A BOR generates a Reset pulse, which resets the

device. The BOR selects the clock source, based on

the device Configuration bit values (FNOSC<2:0> and

POSCMD<1:0>).

If an oscillator mode is selected, the BOR activates the

Oscillator Start-up Timer (OST). The system clock is

held until OST expires. If the PLL is used, the clock is

held until the LOCK bit (OSCCON<5>) is ‘1’.

Concurrently, the PWRT time-out (TPWRT) will be

applied before the internal Reset is released. If TPWRT

= 0 and a crystal oscillator is being used, a nominal

delay of TFSCM = 100 is applied. The total delay in this

case is TFSCM.

The BOR Status bit (RCON<1>) is set to indicate that a

BOR has occurred. The BOR circuit, if enabled, contin-

ues to operate while in Sleep or Idle modes and resets

the device should VDD fall below the BOR threshold

voltage.

Note 1:

These are typical operating voltages. Refer

to TABLE 21-13: “Internal Voltage Regu-

lator Specifications” located in

Section 21.1 “DC Characteristics” for the

full operating ranges of VDD and VDDCORE.

VDD

VDDCORE/VCAP

VSS

PIC24H

3.3V

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